-
1
-
-
34249793560
-
3 etch (SAE) process with nitrogen and fluorine incorporation
-
3 etch (SAE) process with nitrogen and fluorine incorporation," in VLSI Symp. Tech. Dig., 2006, pp. 162-163.
-
(2006)
VLSI Symp. Tech. Dig
, pp. 162-163
-
-
Jung, H.-S.1
Han, S.K.2
Lim, H.3
Kim, Y.-S.4
Kim, M.J.5
Yu, M.Y.6
Lee, C.-K.7
Lee, M.S.8
You, Y.-S.9
Chung, Y.10
Kim, S.11
Baik, H.S.12
Lee, J.-H.13
Lee, N.-I.14
Kang, H.-K.15
-
2
-
-
34249805888
-
Highly manufacturable 45 nm LSTP CMOSFETs using novel dual high-κ and dual metal gate CMOS integration
-
S. C. Song, Z. B. Zhang, M. M. Hussain, C. Huffman, J. Barnett, S. H. Bae, H. J. Li, P. Majhi, C. S. Park, B. S. Ju, H. K. Park, C. Y. Kang, R. Choi, P. Zeitzoff, H. H. Tseng, B. H. Lee, and R. Jammy, "Highly manufacturable 45 nm LSTP CMOSFETs using novel dual high-κ and dual metal gate CMOS integration," in VLSI Symp. Tech. Dig., 2006, pp. 13-14.
-
(2006)
VLSI Symp. Tech. Dig
, pp. 13-14
-
-
Song, S.C.1
Zhang, Z.B.2
Hussain, M.M.3
Huffman, C.4
Barnett, J.5
Bae, S.H.6
Li, H.J.7
Majhi, P.8
Park, C.S.9
Ju, B.S.10
Park, H.K.11
Kang, C.Y.12
Choi, R.13
Zeitzoff, P.14
Tseng, H.H.15
Lee, B.H.16
Jammy, R.17
-
3
-
-
33746521813
-
2 n-MOSFETs
-
Aug
-
2 n-MOSFETs," IEEE Electron Device Lett., vol. 27, no. 8, pp. 640-643, Aug. 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.8
, pp. 640-643
-
-
Lee, T.1
Rhee, S.J.2
Kang, C.Y.3
Zhu, F.4
Kim, H.-S.5
Choi, C.6
Ok, I.7
Zhang, M.8
Krishnan, S.9
Thareja, G.10
Lee, J.C.11
-
4
-
-
33845419668
-
-
H. Alshareef, M. Quevedo-Lopez, H. Wen, R. Harris, P. Kirsch, P. Majhi, B. Lee, R. Jammy, D. Lichtenwalner, J. Jur, and A. Kingon, Work function engineering using lanthanum oxide interfacial layers, Appl. Phys. Lett., 89, no. 23, pp. 232 103-1-232 103-3, Dec. 2006.
-
H. Alshareef, M. Quevedo-Lopez, H. Wen, R. Harris, P. Kirsch, P. Majhi, B. Lee, R. Jammy, D. Lichtenwalner, J. Jur, and A. Kingon, "Work function engineering using lanthanum oxide interfacial layers," Appl. Phys. Lett., vol. 89, no. 23, pp. 232 103-1-232 103-3, Dec. 2006.
-
-
-
-
5
-
-
34249804177
-
3 capping of hafnium silicates
-
Jun
-
3 capping of hafnium silicates," IEEE Electron Device Lett., vol. 28, no. 8, pp. 486-488, Jun. 2007.
-
(2007)
IEEE Electron Device Lett
, vol.28
, Issue.8
, pp. 486-488
-
-
Ragnarsson, L.-Å.1
Chang, V.S.2
Yu, H.Y.3
Cho, H.-J.4
Conard, T.5
Yin, K.M.6
Delabie, A.7
Swerts, J.8
Schram, T.9
De Gendt, S.10
Biesemans, S.11
-
7
-
-
47249087741
-
3 cap layer with either single or dual Ni-phases
-
3 cap layer with either single or dual Ni-phases," in VLSI Symp. Tech. Dig., 2007, pp. 18-19.
-
(2007)
VLSI Symp. Tech. Dig
, pp. 18-19
-
-
Yu, H.Y.1
Chang, S.Z.2
Veloso, A.3
Lauwers, A.4
Adelmann, C.5
Onsia, B.6
Van Elshocht, S.7
Singanamalla, R.8
Demand, M.9
Vos, R.10
Kauerauf, T.11
Brus, S.12
Shi, X.13
Kubicek, S.14
Vrancken, C.15
Mitsuhashi, R.16
Lehnen, P.17
Kittl, J.18
Niwa, M.19
Yin, K.M.20
Hoffmann, T.21
De Gendt, S.22
Jurczak, M.23
Absil, P.24
Biesemans, S.25
more..
-
8
-
-
27944431993
-
Atomic vapour deposition for sub-100 nm CMOS
-
M. Schumacher and J. Linder, "Atomic vapour deposition for sub-100 nm CMOS," Eur. Semicond., vol. 24, pp. 23-29, 2002.
-
(2002)
Eur. Semicond
, vol.24
, pp. 23-29
-
-
Schumacher, M.1
Linder, J.2
-
9
-
-
85069100767
-
-
Hauser CV Analysis Program, Version 5.0, Online, Available
-
Hauser CV Analysis Program, Version 5.0. [Online]. Available: http://www.nnf.ncsu.edu/testing
-
-
-
-
10
-
-
34248633391
-
Performance enhancement of Poly-Si/TiN/SiON based pMOSFETs by addition of an aluminum oxide (AlO) capping layer
-
Sep./Oct
-
R. Singanamalla, H. Yu, B. J. O'Sullivan, J. Petry, A. Mercha, V. Paraschiv, H. Volders, S. Kubicek, K. De Meyer, and S. Biesemans, "Performance enhancement of Poly-Si/TiN/SiON based pMOSFETs by addition of an aluminum oxide (AlO) capping layer," Microelectron. Eng., vol. 84, no. 9/10, pp. 1865-1868, Sep./Oct. 2007.
-
(2007)
Microelectron. Eng
, vol.84
, Issue.9-10
, pp. 1865-1868
-
-
Singanamalla, R.1
Yu, H.2
O'Sullivan, B.J.3
Petry, J.4
Mercha, A.5
Paraschiv, V.6
Volders, H.7
Kubicek, S.8
De Meyer, K.9
Biesemans, S.10
-
11
-
-
44949245167
-
Re-examination of flat-band voltage shift for high-k MOS devices
-
K. Iwamoto, A. Ogawa, Y. Kamimuta, Y. Watanabe, W. Mizubayashi, S. Migita, Y. Morita, M. Takahashi, H. Ito, H. Ota, T. Nabatame, and A. Toriumi, "Re-examination of flat-band voltage shift for high-k MOS devices," in VLSI Symp. Tech. Dig., 2007, pp. 70-71.
-
(2007)
VLSI Symp. Tech. Dig
, pp. 70-71
-
-
Iwamoto, K.1
Ogawa, A.2
Kamimuta, Y.3
Watanabe, Y.4
Mizubayashi, W.5
Migita, S.6
Morita, Y.7
Takahashi, M.8
Ito, H.9
Ota, H.10
Nabatame, T.11
Toriumi, A.12
-
12
-
-
40949130851
-
Dipole moment model explaining nFET Vt tuning utilizing La, Sc, Er, and Sr doped HfSiON dielectrics
-
P. Sivasubramani, T. S. Böscke, J. Huang, C. D. Young, P. D. Kirsch, S. A. Krishnan, M. A. Quevedo-Lopez, S. Govindarajan, B. S. Ju, H. R. Harris, D. J. Lichtenwalner, J. S. Jur, A. I. Kingon, J. Kim, B. E. Gnade, R. M. Wallace, G. Bersuker, B. H. Lee, and R. Jammy, "Dipole moment model explaining nFET Vt tuning utilizing La, Sc, Er, and Sr doped HfSiON dielectrics," in VLSI Symp. Tech. Dig., 2007, pp. 68-69.
-
(2007)
VLSI Symp. Tech. Dig
, pp. 68-69
-
-
Sivasubramani, P.1
Böscke, T.S.2
Huang, J.3
Young, C.D.4
Kirsch, P.D.5
Krishnan, S.A.6
Quevedo-Lopez, M.A.7
Govindarajan, S.8
Ju, B.S.9
Harris, H.R.10
Lichtenwalner, D.J.11
Jur, J.S.12
Kingon, A.I.13
Kim, J.14
Gnade, B.E.15
Wallace, R.M.16
Bersuker, G.17
Lee, B.H.18
Jammy, R.19
|