-
1
-
-
0036907029
-
Subthreshold leakage modeling and reduction techniques
-
J. Kao, S. Narendra, and A. Chandrakasan, "Subthreshold leakage modeling and reduction techniques," Proc. of Int. Conf. on Computer-Aided Design, pp. 141-148, 2002.
-
(2002)
Proc. of Int. Conf. on Computer-aided Design
, pp. 141-148
-
-
Kao, J.1
Narendra, S.2
Chandrakasan, A.3
-
2
-
-
0032592096
-
Design challenges of technology scaling
-
July/Aug
-
S. Borkar, "Design challenges of technology scaling," Micro, pp. 23-29, July/Aug 1999.
-
(1999)
Micro
, pp. 23-29
-
-
Borkar, S.1
-
3
-
-
0030172836
-
Automatic synthesis of low power gated clock finite state machine
-
Jun.
-
L. Benini and G. De Michelli, "Automatic synthesis of low power gated clock finite state machine," Trans. Computer -Aided Design, vol. 15, pp. 630-643, Jun. 1996.
-
(1996)
Trans. Computer -aided Design
, vol.15
, pp. 630-643
-
-
Benini, L.1
De Michelli, G.2
-
4
-
-
0030086605
-
A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme
-
Feb.
-
T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshida, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, T. Sakurai, "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme," in ISSCC Dig. Tech. Papers, pp. 166-167, Feb. 1996.
-
(1996)
ISSCC Dig. Tech. Papers
, pp. 166-167
-
-
Kuroda, T.1
Fujita, T.2
Mita, S.3
Nagamatsu, T.4
Yoshida, S.5
Sano, F.6
Norishima, M.7
Murota, M.8
Kako, M.9
Kinugawa, M.10
Kakumu, M.11
Sakurai, T.12
-
5
-
-
0029359285
-
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
-
Aug.
-
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 8470854, Aug. 1995.
-
(1995)
IEEE Journal of Solid-state Circuits
, vol.30
, Issue.8
, pp. 8470854
-
-
Mutoh, S.1
Douseki, T.2
Matsuya, Y.3
Aoki, T.4
Shigematsu, S.5
Yamada, J.6
-
6
-
-
0242720765
-
Dynamic sleep transistor and body bias for active leakage power control of microprocessors
-
Nov.
-
J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, and S. Borkar, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1838-1843, Nov. 2003.
-
(2003)
IEEE Journal of Solid-state Circuits
, vol.38
, Issue.11
, pp. 1838-1843
-
-
Tschanz, J.1
Narendra, S.2
Ye, Y.3
Bloechel, B.4
Borkar, S.5
-
7
-
-
0038306265
-
Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: An alternative to clock-gating scheme in leakage dominant era
-
Feb.
-
K. S. Min, H. Kawaguchi, and T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," in ISSCC Dig. Tech. Papers, pp.400-401, Feb. 2003.
-
(2003)
ISSCC Dig. Tech. Papers
, pp. 400-401
-
-
Min, K.S.1
Kawaguchi, H.2
Sakurai, T.3
-
8
-
-
0033719725
-
Boosted Gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration
-
May
-
T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration," CICC, pp. 409-412, May 2000.
-
(2000)
CICC
, pp. 409-412
-
-
Inukai, T.1
Takamiya, M.2
Nose, K.3
Kawaguchi, H.4
Hiramoto, T.5
Sakurai, T.6
-
10
-
-
17044426035
-
A regular layout for parallel adders
-
Mar.
-
B. P. Brent and H. T. Kung, "A Regular layout for parallel adders," Trans. on Computers, vol. 12, no. 3, Mar. 1982.
-
(1982)
Trans. on Computers
, vol.12
, Issue.3
-
-
Brent, B.P.1
Kung, H.T.2
-
11
-
-
1542269359
-
Design methodology for fine-grained leakage control in MTCMOS
-
Aug.
-
B. H. Calhoun, F. A. Honore, and A. Chandrakasan, "Design Methodology for Fine-Grained Leakage Control in MTCMOS," in proc. ISLPED, pp. 104-109, Aug. 2003.
-
(2003)
Proc. ISLPED
, pp. 104-109
-
-
Calhoun, B.H.1
Honore, F.A.2
Chandrakasan, A.3
|