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Volumn , Issue , 2004, Pages 87-90

Observation of one-fifth-of-a-clock wake-up time of power-gated circuit

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; LOGIC DESIGN; SIGNAL PROCESSING; TIMING DEVICES;

EID: 17044373463     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (16)

References (11)
  • 2
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    • Design challenges of technology scaling
    • July/Aug
    • S. Borkar, "Design challenges of technology scaling," Micro, pp. 23-29, July/Aug 1999.
    • (1999) Micro , pp. 23-29
    • Borkar, S.1
  • 3
    • 0030172836 scopus 로고    scopus 로고
    • Automatic synthesis of low power gated clock finite state machine
    • Jun.
    • L. Benini and G. De Michelli, "Automatic synthesis of low power gated clock finite state machine," Trans. Computer -Aided Design, vol. 15, pp. 630-643, Jun. 1996.
    • (1996) Trans. Computer -aided Design , vol.15 , pp. 630-643
    • Benini, L.1    De Michelli, G.2
  • 6
    • 0242720765 scopus 로고    scopus 로고
    • Dynamic sleep transistor and body bias for active leakage power control of microprocessors
    • Nov.
    • J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, and S. Borkar, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1838-1843, Nov. 2003.
    • (2003) IEEE Journal of Solid-state Circuits , vol.38 , Issue.11 , pp. 1838-1843
    • Tschanz, J.1    Narendra, S.2    Ye, Y.3    Bloechel, B.4    Borkar, S.5
  • 7
    • 0038306265 scopus 로고    scopus 로고
    • Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: An alternative to clock-gating scheme in leakage dominant era
    • Feb.
    • K. S. Min, H. Kawaguchi, and T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," in ISSCC Dig. Tech. Papers, pp.400-401, Feb. 2003.
    • (2003) ISSCC Dig. Tech. Papers , pp. 400-401
    • Min, K.S.1    Kawaguchi, H.2    Sakurai, T.3
  • 8
    • 0033719725 scopus 로고    scopus 로고
    • Boosted Gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration
    • May
    • T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration," CICC, pp. 409-412, May 2000.
    • (2000) CICC , pp. 409-412
    • Inukai, T.1    Takamiya, M.2    Nose, K.3    Kawaguchi, H.4    Hiramoto, T.5    Sakurai, T.6
  • 10
    • 17044426035 scopus 로고
    • A regular layout for parallel adders
    • Mar.
    • B. P. Brent and H. T. Kung, "A Regular layout for parallel adders," Trans. on Computers, vol. 12, no. 3, Mar. 1982.
    • (1982) Trans. on Computers , vol.12 , Issue.3
    • Brent, B.P.1    Kung, H.T.2
  • 11
    • 1542269359 scopus 로고    scopus 로고
    • Design methodology for fine-grained leakage control in MTCMOS
    • Aug.
    • B. H. Calhoun, F. A. Honore, and A. Chandrakasan, "Design Methodology for Fine-Grained Leakage Control in MTCMOS," in proc. ISLPED, pp. 104-109, Aug. 2003.
    • (2003) Proc. ISLPED , pp. 104-109
    • Calhoun, B.H.1    Honore, F.A.2    Chandrakasan, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.