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46049110549
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High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs
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Nanoscale Germanium MOS Dielectrics-Part I: Germanium Oxynitrides
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CO. Chui, F. Ito, K.C Saraswat, "Nanoscale Germanium MOS Dielectrics-Part I: Germanium Oxynitrides," IEEE Electron Device letters, vol. 53, pp. 1501-1507, July 2006
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IEEE Electron Device letters
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Chui, C.O.1
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46049111464
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Theoretical Investigation of Performance in Uniaxially- and Biaxially-Strained Si, SiGe and Ge Double-gate p-MOSFETs
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T. Krishnamohan, C. Jungemann, D. Kim, E. Ungersboeck, S. Selberherr, P. Wong, Y. Nishi, K. Saraswat, "Theoretical Investigation of Performance in Uniaxially- and Biaxially-Strained Si, SiGe and Ge Double-gate p-MOSFETs," in Proc. IEDM, 2006, pp. 937-940
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39549098321
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0.12μm P-MOSFETs with High-K and Metal Gate Fabricated in a Si Process Line on 200mm GeOI Wafers
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C. Le Royer, L. Clavelier, C. Tabone, C. Deguet, L. Sanchez, J.M. Hartmann, M.C. Roure, H. Grampeix, S. Deleonibus, "0.12μm P-MOSFETs with High-K and Metal Gate Fabricated in a Si Process Line on 200mm GeOI Wafers," Proceedings of ESSDERC, 2007, pp. 458.
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T. Maeda, M. Nishizawa, Y. Morita, Role of germanium nitride interfacial layers in HfD2/germanium nitride/germanium metal-insulator- semiconductor structures, Applied Physics Letters 90, 072911-1-3, 2007
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T. Maeda, M. Nishizawa, Y. Morita, "Role of germanium nitride interfacial layers in HfD2/germanium nitride/germanium metal-insulator- semiconductor structures," Applied Physics Letters vol. 90, 072911-1-3, 2007
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46149119210
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High performance Ge pMOS devices using a Si-compatible process flow
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San Francisco
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P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans,. L.-Å. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, "High performance Ge pMOS devices using a Si-compatible process flow," Proceedings of IEDM, 2006, San Francisco
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Zimmerman, P.1
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Caymax, M.9
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Opsomer, K.11
Meuris, M.12
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Schram, T.1
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9
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39749167824
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On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates
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K. Martens, CO. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. Heyns, T. Krishnamohan, K. Saraswat, H.E. Maes, G. Groeseneken, "On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates," IEEE Transactions on Electron Devices, Vol. 55, no. 2, 2008.
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IEEE Transactions on Electron Devices
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Martens, K.1
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Krishnamohan, T.8
Saraswat, K.9
Maes, H.E.10
Groeseneken, G.11
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10
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34548015238
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Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k metal gate stacks
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P. Batude, X. Garros, L. Clavelier, C. Le Royer, J.M. Hartmann, V. Loup, P. Besson, L. Vandroux, Y. Campidelli, S. Deleonibus, F. Boulanger, "Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k metal gate stacks," J. Appl. Phys., Vol. 102, 034514, 2007
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11
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58149092101
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Optimization of Epitaxial Si Passivation for Ge p-MOSFETs
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paper nr, San Francisco
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J. Mitard, B. De Jaeger, G. Eneman, D.P. Brunco, F.E. Leys, G. Winderickx, G. Pourtois, M. Houssa, M. Meuris, and M. Heyns, "Optimization of Epitaxial Si Passivation for Ge p-MOSFETs," paper nr. 426712, symposium H, MRS Spring Symposium, San Francisco, 2008
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426712, symposium H, MRS Spring Symposium
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Mitard, J.1
De Jaeger, B.2
Eneman, G.3
Brunco, D.P.4
Leys, F.E.5
Winderickx, G.6
Pourtois, G.7
Houssa, M.8
Meuris, M.9
Heyns, M.10
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