0.12μm P-MOSFETs with high-K and metal gate fabricated in a Si process line on 200mm GeOI wafers

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 458-461

  Le Royer, C ^a   Clavelier, L ^a   Tabone, C ^a   Deguet, C ^a   Sanchez, L ^a   Hartmann, J M ^a   Roure, M C ^a   Grampeix, H ^a   Deleonibus, S ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; PROCESS CONTROL; SILICON WAFERS;

FABRICATED DEVICES; GATE STACK; PROCESS LINE;

MOSFET DEVICES;

EID: 39549098321     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430977     Document Type: Conference Paper

References (12)

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