-
2
-
-
0024918789
-
Three dimensional ICs, having four stacked active device layers
-
T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, "Three dimensional ICs, having four stacked active device layers," in IEDM Tech. Dig., 1989, pp. 837-840.
-
(1989)
IEDM Tech. Dig.
, pp. 837-840
-
-
Kunio, T.1
Oyama, K.2
Hayashi, Y.3
Morimoto, M.4
-
3
-
-
0032116366
-
Future system-on-silicon LSI chips
-
Jul./Aug.
-
M. Koyanagi, H. Kurino, K.-W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, "Future system-on-silicon LSI chips," IEEE Micro, vol. 18, no. 4, pp. 17-22, Jul./Aug. 1998.
-
(1998)
IEEE Micro
, vol.18
, Issue.4
, pp. 17-22
-
-
Koyanagi, M.1
Kurino, H.2
Lee, K.-W.3
Sakuma, K.4
Miyakawa, N.5
Itani, H.6
-
4
-
-
0033699518
-
Multiple Si layer ICs: Motivation, performance analysis, and design implications
-
S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat, "Multiple Si layer ICs: Motivation, performance analysis, and design implications," in Proc. 37th ACM Des. Autom. Conf., 2000, pp. 873-880.
-
(2000)
Proc. 37th ACM Des. Autom. Conf.
, pp. 873-880
-
-
Souri, S.J.1
Banerjee, K.2
Mehrotra, A.3
Saraswat, K.C.4
-
5
-
-
33747566850
-
3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
-
May
-
K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.5
, pp. 602-633
-
-
Banerjee, K.1
Souri, S.J.2
Kapur, P.3
Saraswat, K.C.4
-
6
-
-
85001135329
-
Interchip via technology for vertical system integration
-
P. Ramm, D. Bonfert, H. Gieser, J. Haufe, F. Iberl, A. Klumpp, A. Kux, and R.Wieland, "Interchip via technology for vertical system integration," in Proc. IEEE IITC, 2001, pp. 160-162.
-
(2001)
Proc. IEEE IITC
, pp. 160-162
-
-
Ramm, P.1
Bonfert, D.2
Gieser, H.3
Haufe, J.4
Iberl, F.5
Klumpp, A.6
Kux, A.7
Wieland, R.8
-
9
-
-
61549142882
-
3D Integration: Why, what, who, when?
-
J.-Q. Lu, K. Rose, and S. Vitkavage, "3D Integration: Why, what, who, when?," Future Fab Int., no. 23, pp. 25-27, 2007.
-
(2007)
Future Fab Int.
, Issue.23
, pp. 25-27
-
-
Lu, J.-Q.1
Rose, K.2
Vitkavage, S.3
-
10
-
-
0029409492
-
3-D integration of MQW modulators over active submicron CMOS circuits: 375 Mb/s transimpedance receiver-transmitter circuit
-
Nov.
-
A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D'Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. Dahringer, L. M. F. Chirovsky, and D. A. B. Miller, "3-D integration of MQW modulators over active submicron CMOS circuits: 375 Mb/s transimpedance receiver-transmitter circuit," IEEE Photon. Technol. Lett., vol. 7, no. 11, pp. 1288-1290, Nov. 1995.
-
(1995)
IEEE Photon. Technol. Lett.
, vol.7
, Issue.11
, pp. 1288-1290
-
-
Krishnamoorthy, A.V.1
Lentine, A.L.2
Goossen, K.W.3
Walker, J.A.4
Woodward, T.K.5
Ford, J.E.6
Aplin, G.F.7
D'Asaro, L.A.8
Hui, S.P.9
Tseng, B.10
Leibenguth, R.11
Kossives, D.12
Dahringer, D.13
Chirovsky, L.M.F.14
Miller, D.A.B.15
-
11
-
-
0036228244
-
3-D integrable optoelectronic devices for telecommunications ICs
-
P. Dainesi, A. M. Ionescu, L. Thevenaz, K. Banerjee, M. J. Declercq, P. Robert, P. Renaud, P. Fluckiger, C. Hilbert, and G. A. Racine, "3-D integration optoelectronics devices for telecommunication ICs," in Proc. IEEE ISSCC, 2002, pp. 290-291. (Pubitemid 34434778)
-
(2002)
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
, Issue.SUPPL.
, pp. 290-291
-
-
Dainesi, P.1
Ionescu, A.M.2
Thevenaz, L.3
Banerjee, K.4
Declercq, M.J.5
Robert, P.6
Renaud, P.7
Fluckiger, P.8
Hibert, C.9
Racine, G.A.10
-
12
-
-
42149124250
-
Monolithic integration of photonic and electronic circuits in a CMOS process
-
A. Mekis, S. Abdalla, B. Analui, S. Gloeckner, A. Guckenberger, K.Koumans, D.Kucharski,Y. Liang, G. Masini, S.Mirsaidi, A. Narasimha, T. Pinguet, V. Sadagopan, B.Welch, J.White, and J.Witzens, "Monolithic integration of photonic and electronic circuits in a CMOS process," Proc. SPIE, vol. 6897, p. 689 70L, 2008.
-
(2008)
Proc. SPIE
, vol.6897
-
-
Mekis, A.1
Abdalla, S.2
Analui, B.3
Gloeckner, S.4
Guckenberger, A.5
Koumans, K.6
Kucharski, D.7
Liang, Y.8
Masini, G.9
Mirsaidi, S.10
Narasimha, A.11
Pinguet, T.12
Sadagopan, V.13
Welch, B.14
White, J.15
Witzens, J.16
-
13
-
-
41549156886
-
High-throughput silicon nanophotonic deflection switch for on-chip optical networks
-
Y. Vlasov, W. Green, and F. Xia, "High-throughput silicon nanophotonic deflection switch for on-chip optical networks," Nat. Photon., vol. 2, pp. 242-246, 2008.
-
(2008)
Nat. Photon.
, vol.2
, pp. 242-246
-
-
Vlasov, Y.1
Green, W.2
Xia, F.3
-
14
-
-
70449369305
-
Device technology innovation for exascale computing
-
T.-C. Chen, "Device technology innovation for exascale computing," in VLSI Symp. Tech. Dig., 2009, pp. 8-11.
-
(2009)
VLSI Symp. Tech. Dig.
, pp. 8-11
-
-
Chen, T.-C.1
-
15
-
-
62349108063
-
Technologies for 3D wafer level heterogeneous integration
-
M. Wolf, P. Ramm, A. Klumpp, and H. Reichl, "Technologies for 3D wafer level heterogeneous integration," in Proc. DTIP MEMS/MOEMS, 2008, pp. 123-126.
-
(2008)
Proc. DTIP MEMS/MOEMS
, pp. 123-126
-
-
Wolf, M.1
Ramm, P.2
Klumpp, A.3
Reichl, H.4
-
16
-
-
71049175802
-
Alternative approach in 3D MEMS-IC integration using fluidic self-assembly techniques
-
Oct.
-
Y. Chapuis, A. Debray, L. Jalabert, H. Fujita, and S. Cheramy, "Alternative approach in 3D MEMS-IC integration using fluidic self-assembly techniques," J. Micromech. Microeng., vol. 19, no. 10, p. 105 002, Oct. 2009.
-
(2009)
J. Micromech. Microeng.
, vol.19
, Issue.10
, pp. 105002
-
-
Chapuis, Y.1
Debray, A.2
Jalabert, L.3
Fujita, H.4
Cheramy, S.5
-
17
-
-
70349469833
-
New trends in wafer level packaging
-
N. Sillon, D. Henry, J. Souriau, J. Brun, H. Boutry, and S. Cheramy, "New trends in wafer level packaging," in Proc. Int. Interconnect Technol. Conf., 2009, pp. 211-213.
-
(2009)
Proc. Int. Interconnect Technol. Conf.
, pp. 211-213
-
-
Sillon, N.1
Henry, D.2
Souriau, J.3
Brun, J.4
Boutry, H.5
Cheramy, S.6
-
18
-
-
79952039233
-
The challenges of future automotive HMI design: Overview of the AIDE integrated project
-
J. Engström, J. Arfwidsson, A. Amditis, L. Andreone, K. Bengler, P. C. Cacciabue, J. Eschler, F. Nathan, and W. H. Janssen, "The challenges of future automotive HMI design: Overview of the AIDE integrated project," in Proc. ITS Eur., 2004.
-
(2004)
Proc. ITS Eur.
-
-
Engström, J.1
Arfwidsson, J.2
Amditis, A.3
Andreone, L.4
Bengler, K.5
Cacciabue, P.C.6
Eschler, J.7
Nathan, F.8
Janssen, W.H.9
-
20
-
-
0242493154
-
Performance constraints for on chip optical interconnects
-
Mar./Apr.
-
J. H. Collet, F. Caignet, F. Sellaye, and D. Litaize, "Performance constraints for on chip optical interconnects," IEEE J. Sel. Topics Quantum Electron., vol. 9, no. 2, pp. 425-432, Mar./Apr. 2003.
-
(2003)
IEEE J. Sel. Topics Quantum Electron.
, vol.9
, Issue.2
, pp. 425-432
-
-
Collet, J.H.1
Caignet, F.2
Sellaye, F.3
Litaize, D.4
-
21
-
-
33646751859
-
Integration issues of a photonic interconnections on CMOS circuit
-
J.-M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, "Integration issues of a photonic interconnections on CMOS circuit," in Proc. SPIE Photon. Eur., 2006, vol. 6125, pp. 97-111.
-
(2006)
Proc. SPIE Photon. Eur.
, vol.6125
, pp. 97-111
-
-
Fedeli, J.-M.1
Orobtchouk, R.2
Seassal, C.3
Vivien, L.4
-
22
-
-
33845669875
-
A fully integrated 20-Gb/s optoelectronic transceiver implemented in a standard 0.13-μm CMOS SOI technology
-
DOI 10.1109/JSSC.2006.884388
-
B. Analui, D. Guckenberger, D. Kucharski, and A. Narasimha, "A fully integrated 20-Gb/s optoelectronic transceiver implemented in a standard 0.13- μm CMOS SOI technology," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2945-2955, Dec. 2006. (Pubitemid 44955519)
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.12
, pp. 2945-2955
-
-
Analui, B.1
Guckenberger, D.2
Kucharski, D.3
Narasimha, A.4
-
23
-
-
34547455222
-
Systematic simulation-based predictive synthesis of integrated optical interconnect
-
Aug.
-
I. O'Connor, F. Tissafi-Drissi, F. Gaffiot, J. Dambre, M. D. Wilde, J. V. Campenhout, D. V. Thourhout, J. V. Campenhout, and D. Stroobandt, "Systematic simulation-based predictive synthesis of integrated optical interconnect," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 8, pp. 927-940, Aug. 2007.
-
(2007)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.15
, Issue.8
, pp. 927-940
-
-
O'Connor, I.1
Tissafi-Drissi, F.2
Gaffiot, F.3
Dambre, J.4
Wilde, M.D.5
Campenhout, J.V.6
Thourhout, D.V.7
Campenhout, J.V.8
Stroobandt, D.9
-
24
-
-
0032206740
-
Advances in silicon-on-insulator optoelectronics
-
PII S1077260X98091254
-
B. Jalali, S. Yegnanarayanan, T. Yoon, T. Yoshimoto, I. Rendian, and F. Coppinger, "Advances in silicon-on-insulator optoelectronics," IEEE J. Sel. Topics Quantum Electron., vol. 4, no. 6, pp. 938-947, Nov./Dec. 1998. (Pubitemid 128566881)
-
(1998)
IEEE Journal on Selected Topics in Quantum Electronics
, vol.4
, Issue.6
, pp. 938-947
-
-
Jalali, B.1
Yegnanarayanan, S.2
Yoon, T.3
Yoshimoto, T.4
Rendina, I.5
Coppinger, F.6
-
25
-
-
39749086538
-
Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides
-
DOI 10.1364/OL.32.002801
-
W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, "Low-loss, lowcross-talk crossing for silicon-on-insulator nanophotonic waveguides," Opt. Lett., vol. 32, no. 19, pp. 2801-2803, Oct. 2007. (Pubitemid 351302883)
-
(2007)
Optics Letters
, vol.32
, Issue.19
, pp. 2801-2803
-
-
Bogaerts, W.1
Dumon, P.2
Van Thourhout, D.3
Baets, R.4
-
26
-
-
4944228235
-
Multi-voltage SOI-BiCMOS for 14 v & 42 v automotive applications
-
F. Kawai, T. Onishi, T. Kamiya, H. Ishimabushi, H. Eguchi, K. Nakahama, H. Aoki, and K. Hamada, "Multi-voltage SOI-BiCMOS for 14 V & 42 V automotive applications," in Proc. ISPSD, 2004, pp. 165-168.
-
(2004)
Proc. ISPSD
, pp. 165-168
-
-
Kawai, F.1
Onishi, T.2
Kamiya, T.3
Ishimabushi, H.4
Eguchi, H.5
Nakahama, K.6
Aoki, H.7
Hamada, K.8
-
27
-
-
51349085624
-
Robust hermetic wafer level thin film encapsulation technology for stacked MEMS/IC package
-
Y. Shimooka, M. Inoue, M. Endo, S. Obata, A. Kojima, T. Miyagi, I. Mori, and H. Shibata, "Robust hermetic wafer level thin film encapsulation technology for stacked MEMS/IC package," in Proc. ECTC, 2008, pp. 824-828.
-
(2008)
Proc. ECTC
, pp. 824-828
-
-
Shimooka, Y.1
Inoue, M.2
Endo, M.3
Obata, S.4
Kojima, A.5
Miyagi, T.6
Mori, I.7
Shibata, H.8
-
28
-
-
70349205855
-
Investigation of key technologies for system-in-package integration of inertial MEMS
-
N. Marenco, W. Reinert, S. Warnat, P. Lange, S. Gruenzig, G. Allegato, G. Hillmann, H. Kostner, W. Gal, S. Guadagnuolo, A. Conte, K. Malecki, and K. Friedel, "Investigation of key technologies for system-in-package integration of inertial MEMS," in Proc. DTIP MEMS/MOEMS, 2009, pp. 35-40.
-
(2009)
Proc. DTIP MEMS/MOEMS
, pp. 35-40
-
-
Marenco, N.1
Reinert, W.2
Warnat, S.3
Lange, P.4
Gruenzig, S.5
Allegato, G.6
Hillmann, G.7
Kostner, H.8
Gal, W.9
Guadagnuolo, S.10
Conte, A.11
Malecki, K.12
Friedel, K.13
-
29
-
-
65949104077
-
Development of multi-user multi-chip SOI CMOSMEMS processes
-
K. Takahashi, M. Mita, M. Nakada, D. Yamane, A. Higo, H. Fujita, and H. Toshiyoshi, "Development of multi-user multi-chip SOI CMOSMEMS processes," in Proc. MEMS, 2009, pp. 701-704.
-
(2009)
Proc. MEMS
, pp. 701-704
-
-
Takahashi, K.1
Mita, M.2
Nakada, M.3
Yamane, D.4
Higo, A.5
Fujita, H.6
Toshiyoshi, H.7
-
30
-
-
50249134337
-
Integrated MEMS LC resonator with sealed air-suspended structure for single-chip RF LSIs
-
K. Kuwabara, N. Sato, H.Morimura, J. Kodate, M. Nakamura,M. Ugajin, T. Kamei, K. Kudou, K. Machida, and H. Ishii, "Integrated MEMS LC resonator with sealed air-suspended structure for single-chip RF LSIs," in IEDM Tech. Dig., 2007, pp. 423-426.
-
(2007)
IEDM Tech. Dig.
, pp. 423-426
-
-
Kuwabara, K.1
Sato, N.2
Morimura, H.3
Kodate, J.4
Nakamura, M.5
Ugajin, M.6
Kamei, T.7
Kudou, K.8
MacHida, K.9
Ishii, H.10
-
31
-
-
0343166147
-
A new wafer scale chip-on-chip (W-COC) packaging technology using adhesive injection method
-
H. Kurino, K.-W. Lee, K. Sakuma, T. Nakamura, and M. Koyanagi, "A new wafer scale chip-on-chip (W-COC) packaging technology using adhesive injection method," Jpn. J. Appl. Phys., vol. 38, no. 4B, pp. 2406-2410, Apr. 1999. (Pubitemid 129697723)
-
(1999)
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
, vol.38
, Issue.4 B
, pp. 2406-2410
-
-
Kurino, H.1
Lee, K.W.2
Sakuma, K.3
Nakamura, T.4
Koyanagi, M.5
-
32
-
-
0033717508
-
Development of three dimensional integration technology for highly parallel image processing chip
-
Apr.
-
K.-W. Lee, T. Nakamura, K. Sakuma, K.-T. Park, H. Shimazutsu, N. Miyakawa, K.-Y. Kim, H. Kurino, and M. Koyanagi, "Development of three dimensional integration technology for highly parallel image processing chip," Jpn. J. Appl. Phys., vol. 39, no. 4B, pp. 2473-2477, Apr. 2000.
-
(2000)
Jpn. J. Appl. Phys.
, vol.39
, Issue.4 B
, pp. 2473-2477
-
-
Lee, K.-W.1
Nakamura, T.2
Sakuma, K.3
Park, K.-T.4
Shimazutsu, H.5
Miyakawa, N.6
Kim, K.-Y.7
Kurino, H.8
Koyanagi, M.9
-
33
-
-
0034453365
-
Three dimensional shared memory fabricated using wafer stacking technology
-
K.-W. Lee, T. Nakamura, T. Ono, Y. Yamada, H. Hashimoto, K.-T. Park, H. Kurino, and M. Koyanagi, "Three dimensional shared memory fabricated using wafer stacking technology," in IEDM Tech. Dig., 2000, pp. 165-186.
-
(2000)
IEDM Tech. Dig.
, pp. 165-186
-
-
Lee, K.-W.1
Nakamura, T.2
Ono, T.3
Yamada, Y.4
Hashimoto, H.5
Park, K.-T.6
Kurino, H.7
Koyanagi, M.8
-
34
-
-
0035054823
-
Neuromorphic vision chip fabricated using three-dimensional integration technology
-
M. Koyanagi, Y. Nakagawa, K.-W. Lee, T. Nakamura, Y. Yamada, K. Inamura, K.-T. Park, and H. Kurino, "Neuromorphic vision chip fabricated using three-dimensional integration technology," in Proc. IEEE ISSCC, 2001, pp. 270-271.
-
(2001)
Proc. IEEE ISSCC
, pp. 270-271
-
-
Koyanagi, M.1
Nakagawa, Y.2
Lee, K.-W.3
Nakamura, T.4
Yamada, Y.5
Inamura, K.6
Park, K.-T.7
Kurino, H.8
-
35
-
-
33750592887
-
Three-dimensional integration technology based on wafer bonding with vertical buried interconnections
-
DOI 10.1109/TED.2006.884079
-
M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino, "Three-dimensional integration technology based on wafer bonding with vertical buried interconnections," IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2799-2808, Nov. 2006. (Pubitemid 44680677)
-
(2006)
IEEE Transactions on Electron Devices
, vol.53
, Issue.11
, pp. 2799-2808
-
-
Koyanagi, M.1
Nakamura, T.2
Yamada, Y.3
Kikuchi, H.4
Fukushima, T.5
Tanaka, T.6
Kurino, H.7
-
36
-
-
33847732625
-
New three-dimensional integration technology using self-assembly technique
-
1609347, IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
-
T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, "New threedimensional integration technology using self-assembly technique," in IEDM Tech. Dig., 2005, pp. 348-351. (Pubitemid 46370861)
-
(2005)
Technical Digest - International Electron Devices Meeting, IEDM
, vol.2005
, pp. 348-351
-
-
Fukushima, T.1
Yamada, Y.2
Kikuchi, H.3
Koyanagi, M.4
-
37
-
-
50249183988
-
New three-dimensional integration technology based on reconfigured wafer-on-wafer bonding technique
-
T. Fukushima, H. Kikuchi, Y. Yamada, T. Konno, J. Liang, K. Sasaki, K. Inamura, T. Tanaka, and M. Koyanagi, "New three-dimensional integration technology based on reconfigured wafer-on-wafer bonding technique," in IEDM Tech. Dig., 2007, pp. 985-988.
-
(2007)
IEDM Tech. Dig.
, pp. 985-988
-
-
Fukushima, T.1
Kikuchi, H.2
Yamada, Y.3
Konno, T.4
Liang, J.5
Sasaki, K.6
Inamura, K.7
Tanaka, T.8
Koyanagi, M.9
-
38
-
-
64549128118
-
New heterogeneous multi-chip module integration technology using self-assembly method
-
T. Fukushima, T. Konno, K. Kiyoyama, M. Murugesan, K. Sato, W.-C. Jeong, Y. Ohara, A. Noriki, S. Kanno, Y. Kaiho, H. Kino, K. Makita, R. Kobayashi, C.-K. Yin, K.-W. Lee, J.-C. Bea, T. Tanaka, and M. Koyanagi, "New heterogeneous multi-chip module integration technology using self-assembly method," in IEDM Tech. Dig., 2008, pp. 499-502.
-
(2008)
IEDM Tech. Dig.
, pp. 499-502
-
-
Fukushima, T.1
Konno, T.2
Kiyoyama, K.3
Murugesan, M.4
Sato, K.5
Jeong, W.-C.6
Ohara, Y.7
Noriki, A.8
Kanno, S.9
Kaiho, Y.10
Kino, H.11
Makita, K.12
Kobayashi, R.13
Yin, C.-K.14
Lee, K.-W.15
Bea, J.-C.16
Tanaka, T.17
Koyanagi, M.18
-
39
-
-
70349690970
-
The formation of lateral interconnections extending over 100-mm-thick chips
-
M. Murugesan, J. C. Bea, S. Y. Ji, C. K. Yin, K. Kiyoyama, T. Konno, H. Kino, Y. Ohara, T. Fukushima, T. Tanaka, and M. Koyanagi, "The formation of lateral interconnections extending over 100-mm-thick chips," in Proc. Ext. Abstr. Solid State Devices Mater., 2008, pp. 472-473.
-
(2008)
Proc. Ext. Abstr. Solid State Devices Mater.
, pp. 472-473
-
-
Murugesan, M.1
Bea, J.C.2
Ji, S.Y.3
Yin, C.K.4
Kiyoyama, K.5
Konno, T.6
Kino, H.7
Ohara, Y.8
Fukushima, T.9
Tanaka, T.10
Koyanagi, M.11
-
40
-
-
78649678945
-
High-aspect-ratio fine Cu sidewall interconnection over chip edge with tapered polymer for MEMS-LSI multi-chip module
-
A. Noriki, Y. Kaiho, E. Iwata, Y. Ohara, M. Murugesan, K. W. Lee, J. C. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi, "High-aspect-ratio fine Cu sidewall interconnection over chip edge with tapered polymer for MEMS-LSI multi-chip module," in Proc. Int. Conf. Solid State Devices Mater., 2009, pp. 88-89.
-
(2009)
Proc. Int. Conf. Solid State Devices Mater.
, pp. 88-89
-
-
Noriki, A.1
Kaiho, Y.2
Iwata, E.3
Ohara, Y.4
Murugesan, M.5
Lee, K.W.6
Bea, J.C.7
Fukushima, T.8
Tanaka, T.9
Koyanagi, M.10
-
41
-
-
79952041353
-
Hetero-integration technology for 3D MEMS/LSI super chip
-
Sep.
-
K.-W. Lee, S. Kanno, Y. Ohara, K. Kiyoyama, J-C. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi, "Hetero-integration technology for 3D MEMS/LSI super chip," in Proc. IEEE Int. 3D Syst. Integr. Conf., Sep. 2009.
-
(2009)
Proc. IEEE Int. 3D Syst. Integr. Conf.
-
-
Lee, K.-W.1
Kanno, S.2
Ohara, Y.3
Kiyoyama, K.4
Bea, J.-C.5
Fukushima, T.6
Tanaka, T.7
Koyanagi, M.8
-
42
-
-
73449098888
-
Novel interconnection technology for heterogeneous integration of MEMS-LSI multi-chip module
-
Mar.
-
K.-W. Lee and M. Koyanagi, "Novel interconnection technology for heterogeneous integration of MEMS-LSI multi-chip module," Microsyst. Technol., vol. 16, no. 3, pp. 441-447, Mar. 2010.
-
(2010)
Microsyst. Technol.
, vol.16
, Issue.3
, pp. 441-447
-
-
Lee, K.-W.1
Koyanagi, M.2
-
43
-
-
79952037446
-
Passive optical alignment with high accuracy for low-loss optical interposer
-
M. Fujiwara, S. Terada, Y. Shirato, H. Owari, K. Watanabe, M. Matsuyama, K. Takahama, T. Mori, K. Miyao, K. Choki, T. Fukushima, T. Tanaka, and M. Koyanagi, "Passive optical alignment with high accuracy for low-loss optical interposer," in Proc. Ext. Abstr. Int. Conf. Solid State Devices Mater., 2007, pp. 988-989.
-
(2007)
Proc. Ext. Abstr. Int. Conf. Solid State Devices Mater.
, pp. 988-989
-
-
Fujiwara, M.1
Terada, S.2
Shirato, Y.3
Owari, H.4
Watanabe, K.5
Matsuyama, M.6
Takahama, K.7
Mori, T.8
Miyao, K.9
Choki, K.10
Fukushima, T.11
Tanaka, T.12
Koyanagi, M.13
-
44
-
-
54249097875
-
Low-loss optical interposer with recessed vertical-cavity surface-emitting laser diode and photodiode chips into Si substrate
-
Apr.
-
M. Fujiwara, S. Terada, Y. Shirato, H. Owari, K. Watanabe, M. Matsuyama, K. Takahama, T. Mori, K. Miyao, K. Choki, T. Fukushima, T. Tanaka, and M. Koyanagi, "Low-loss optical interposer with recessed vertical-cavity surface-emitting laser diode and photodiode chips into Si substrate," Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2936-2940, Apr. 2008.
-
(2008)
Jpn. J. Appl. Phys.
, vol.47
, Issue.4
, pp. 2936-2940
-
-
Fujiwara, M.1
Terada, S.2
Shirato, Y.3
Owari, H.4
Watanabe, K.5
Matsuyama, M.6
Takahama, K.7
Mori, T.8
Miyao, K.9
Choki, K.10
Fukushima, T.11
Tanaka, T.12
Koyanagi, M.13
-
45
-
-
77952471764
-
Optical interposer technology using buried VCSEL and tapered TSV for high-speed chip-to-chip optical interconnection
-
Apr.
-
A. Noriki,M. Fujiwara, K.WLee,W.-C. Jeong, T. Fukushima, T. Tanaka, and M. Koyanagi, "Optical interposer technology using buried VCSEL and tapered TSV for high-speed chip-to-chip optical interconnection," Jpn. J. Appl. Phys., vol. 48, no. 4, p. 04C 113, Apr. 2009.
-
(2009)
Jpn. J. Appl. Phys.
, vol.48
, Issue.4
-
-
Noriki, A.1
Fujiwara, M.2
Lee, K.W.3
Jeong, W.-C.4
Fukushima, T.5
Tanaka, T.6
Koyanagi, M.7
-
46
-
-
84962252719
-
Development of EEB (Electroplated-Evaporation Bumping) technology for fine pitch and low resistance Cu/Sn micro-bumps
-
Oct. 7
-
Y. Ohara, A. Noriki, E. Iwata, T. Hiraki, K. W. Lee, M. Murugesan, J. C. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi, "Development of EEB (Electroplated-Evaporation Bumping) technology for fine pitch and low resistance Cu/Sn micro-bumps," in Proc. Int. Conf. SSDM, Oct. 7, 2009, pp. 86-87.
-
(2009)
Proc. Int. Conf. SSDM
, pp. 86-87
-
-
Ohara, Y.1
Noriki, A.2
Iwata, E.3
Hiraki, T.4
Lee, K.W.5
Murugesan, M.6
Bea, J.C.7
Fukushima, T.8
Tanaka, T.9
Koyanagi, M.10
-
47
-
-
77952495048
-
Characteristics of copper spiral inductors utilizing FePt nanodot films
-
Apr.
-
W.-C. Jeong, K. Kiyoyama, K.-W. Lee, A. Noriki, M. Murugesan, T. Fukushima, T. Tanaka, and M. Koyanagi, "Characteristics of copper spiral inductors utilizing FePt nanodot films," Jpn. J. Appl. Phys., vol. 48, no. 4, pp. 04C 157-1-04C 157-4, Apr. 2009.
-
(2009)
Jpn. J. Appl. Phys.
, vol.48
, Issue.4
-
-
Jeong, W.-C.1
Kiyoyama, K.2
Lee, K.-W.3
Noriki, A.4
Murugesan, M.5
Fukushima, T.6
Tanaka, T.7
Koyanagi, M.8
|