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Volumn , Issue , 2008, Pages 123-126
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Technologies for 3D wafer level heterogeneous integration
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Author keywords
[No Author keywords available]
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Indexed keywords
3-D ARCHITECTURES;
3-D INTEGRATIONS;
ELECTRICAL PERFORMANCE;
FORM FACTORS;
FRAUNHOFER;
HETEROGENEOUS INTEGRATIONS;
HIGH-DENSITY INTERCONNECTS;
ON WAFERS;
REDISTRIBUTION LAYERS;
TECHNOLOGY PORTFOLIOS;
THROUGH-SILICON VIAS;
WAFER LEVELS;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
APPROXIMATION THEORY;
CHIP SCALE PACKAGES;
MEMS;
MICROELECTROMECHANICAL DEVICES;
SEMICONDUCTING SILICON COMPOUNDS;
TECHNOLOGY;
SILICON WAFERS;
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EID: 62349108063
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/DTIP.2008.4752966 Document Type: Conference Paper |
Times cited : (48)
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References (11)
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