Development of three-dimensional integration technology for highly parallel image-processing chip

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 39, Issue 4 B, 2000, Pages 2473-2477

  Lee, Kang Wook ^a   Nakamura, Tomonori ^a   Sakuma, Katsuyuki ^a   Park, Ki Tae ^a   Shimazutsu, Hiroaki ^b   Miyakawa, Nobuaki ^c   Kim, Ki Yoon ^d   Kurino, Hiroyuki ^a   Koyanagi, Mitsumasa ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b MITSUBISHI HEAVY INDUSTRIES LTD   (Japan)

^c XEROX CORPORATION   (United States)

^d JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

Image sensor; Three dimensional (3D) integration LSI; Wafer level bonding

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; IMAGE SENSORS; PHOTODIODES; SILICON WAFERS;

THREE DIMENSIONAL INTEGRATION; WAFER LEVEL BONDING;

LSI CIRCUITS;

EID: 0033717508     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.39.2473     Document Type: Article

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