New trends in wafer level packaging

Proceedings of the 2009 IEEE International Interconnect Technology Conference, IITC 2009

Volumn , Issue , 2009, Pages 211-213

  Sillon, N ^a   Henry, D ^a   Souriau, J C ^a   Brun, J ^a   Boutry, H ^a   Cheramy, S ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BELT TECHNOLOGY; DIE SIZE; END USERS; GENERIC TECHNOLOGY; HETEROGENEOUS SYSTEMS; INTEGRATION SCHEME; WAFER LEVEL PACKAGING; WAFER-LEVEL INTEGRATION;

BUILDING MATERIALS; SILICON WAFERS; TECHNOLOGY;

ELECTRONICS PACKAGING;

EID: 70349469833     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2009.5090390     Document Type: Conference Paper

References (13)

1. A. Mathewson. et al., "Microstructured Interconnections" ESTC 2006.
2. A. Mathewson, et al., "Ni Microinsert Technology" ECTC 2007.
3. H.Boutry. et al, Reliability characterization of Ni-based microinsert 10th Electronic Packaging Technology Conf, Singapore, Dec 2008
4. J.Brun et al., 3D Via Belt Technology, " 59th ECTC, San Diego, 2009.
5. K.D Gann "Neo-Staking technology"issue of HDI Magazine, Dec 1999
6. J-C Souriau et al "Wafer Level Processing Of 3D System In Package " 55th Electronic Comp. and Techno. Conf, Orlando, 2005, pp.356-361.
7. E Fürgut "Taking Wafer Level Packaging to the Next Stage" Advanced Packaging Conference SEMICON Europa 2006, Munich, Germany
8. J-C Souriau et al, Chip In Wafer for Integrated System, 10th EPTC Conf, Singapore, Dec 2008,
9. A.Jouve, "Ultrathin Wafer Handling for TSV", EPTC 2008
10. D.Henry., "TSV Technology for CIS Packaging", ECTC 2008,p. 556
11. J.Charbonnier et al., Integration of a Temporary Carrier in a TSV Process Flow, ECTC 2009
12. S.Cheramy & al., To be published in EMPC 2009
13. N. Sillon et Al , 3S workshop 2006 , Atlanta