Optical interposer technology using buried vertical-cavity surface-emitting laser chip and tapered through-silicon via for high-speed chip-to-chip optical interconnection

Japanese Journal of Applied Physics

Volumn 48, Issue 4 PART 2, 2009, Pages

  Noriki, Akihiro ^a,b   Fujiwara, Makoto ^a,b   Lee, Kang Wook ^a   Jeong, Woo Cheol ^a   Fukushima, Takafumi ^a   Tanaka, Tetsu ^a   Koyanagi, Mitsumasa ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b Sumitomo Bakelite Co Ltd ^*  (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BASIC OPERATION; COPPER ELECTROPLATING; HIGH-SPEED CHIPS; LSI CHIPS; MOLTEN SOLDERS; OPTICAL INTERCONNECTIONS; PASSIVE ALIGNMENT; POLYMERIC OPTICAL WAVEGUIDES; THREE-DIMENSIONAL (3D); THROUGH SILICON VIAS; VERTICAL-CAVITY SURFACE EMITTING LASER;

ALIGNMENT; ELECTRONICS PACKAGING; LASERS; OPTICAL INTERCONNECTS; OPTICAL WAVEGUIDES; THREE DIMENSIONAL; WAVEGUIDES;

SURFACE EMITTING LASERS;

EID: 77952471764     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.48.04C113     Document Type: Article

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