Dual-Vth independent-gate FinFETs for low power logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 3, 2011, Pages 337-349

  Rostami, Masoud ^a   Mohanram, Kartik ^a  

^a Rice University   (United States)

Author keywords

Double gate; dual Vth; FinFET; low power design; technology mapping; transistor

Indexed keywords

DOUBLE-GATE; DUAL-VTH; FINFET; LOW-POWER DESIGN; TECHNOLOGY MAPPING;

BOOLEAN FUNCTIONS; COMPUTER SIMULATION; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LOGIC GATES; OPTIMIZATION; SWITCHING CIRCUITS; TECHNOLOGY;

LOGIC CIRCUITS;

EID: 79951917300     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2097310     Document Type: Article

References (36)

1. J. Colinge, FinFETsand OtherMulti-Gate Transistors. Berlin, Germany: Springer, Nov. 2007.
2. X. Huang, W.-C. Lee, C Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C Hu, "Sub-50nm p-channel FinFET," IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 880-886, May 2001.
3. L. Mathew, Y Du, A. V.-Y. Thean, M. Sadd, A. Vandooren, C Parker, T. Stephens, R. Mora, R. Rai, M. Zavala, D. Sing, S. Kalpat, J. Hughes, R. Shimer, S. Jallepalli, G. Workman, W. Zhang, J. G. Fossum, B. E. White, B.-Y Nguyen, and J. Mogab, "CMOS vertical multiple independent gate field effect transistor (MIGFET)," in Proc IEEE Int. SOI Conf., Oct. 2004, pp. 187-189. (Pubitemid 40455167)
4. Y Q. Wu, R. S. Wang, T. Shen, J. J. Gu, and P. D. Ye, "First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching," in Proc IEDM, 2009, pp. 1-4.
5. L. Mathew, L. Y Du, S. Kaipat, M. Sadd, M. Zavala, T. Stephens, R. Mora, R. Rai, S. Becker, C Parker, D. Sing, R. Shimer, J. Sanez, A. V. Y Thean, L. Prabhu, M. Moosa, B. Y Nguyen, J. Mogah, G. O. Workman, A. Vandooren, Z. Shi, M. M. Chowdhury, W. Zhang, and J. G. Fossum, "Multiple independent gate field effect transistor (MIGFET): Multi-fin RF mixer architecture, three independent gates (MIGFET-T) operation and temperature characteristics," in Proc Int. Symp. VLSI Technol., 2005, pp. 200-201. (Pubitemid 43897623)
6. A. Datta, A. Goel, R. T. Cakici, H. Mahmoodi, D. Lekshmanan, and K. Roy, "Modeling and circuit synthesis for independently controlled double gate FinFET devices," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 11, pp. 1957-1966, Nov. 2007.
7. A. Muttreja, N. Agarwal, and N. K. Jha, "CMOS logic design with independent-gate FinFETs," in Proc Int. Conf. Comput. Design, 2007, pp. 560-567.
8. R. Cakici and K. Roy, "Analysis of options in double-gate MOS tech-nology: A circuit perspective," IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3361-3368, Dec 2007. (Pubitemid 350225943)
9. S. Tawfik and V. Kursun, "FinFET domino logic with independent gate keepers," Microelectron. J., vol. 40, no. 11, pp. 1531-1540, 2009.
10. S. H. Rasouli, H. Koinke, and K. Banerjee, "High-speed low-power FinFET based domino logic," in Proc Asia South Pacific Design Autom. Conf., 2009, pp. 829-834.
11. W. Zhang, J. G. Fossum, L. Mathew, and Y Du, "Physical insights regarding design and performance of independent-gate FinFETs," IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2198-2206, Oct. 2005.
12. Synopsys Sentaurus Design Suite, Synopsys, Mountain View, CA, 2009.
13. M. Rostami and K. Mohanram, "Novel dual-Vth independent-gate FinFET circuits," in Proc Asia South Pacific Des. Automat Conf., 2010, pp. 867-872.
14. S. Nuttinck, B. Parvais, G. Curatola, and A. Mercha, "Double-gate FinFETs as a CMOS technology downscaling option: An RF perspective," IEEE Trans. Electron Devices, vol. 54, no. 2, pp. 279-283, Feb. 2007. (Pubitemid 46358412)
15. Y. Cao and W. Zhao, "Predictive technology model for nano-CMOS design exploration," in Proc Int. Conf. Nano-Netw., 2006, pp. 1-5.
16. M. V. Dunga, C.-H. Lin, D. D. Lu, W. Xiong, C R. Cleavelin, P. Patruno, J.-R. Hwang, F.-L. Yang, A. M. Niknejad, and H. Chenming, "BSIMMG: A versatile multi-gate FET model for mixed-signal design," in Proc IEEE Symp. VLSI Tech., Jun. 2007, pp. 60-61.
17. M.-H. Chiang, K. Kim, C.-T. Chuang, and C Tretz, "High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2370-2377, Sep. 2006. (Pubitemid 46405167)
18. J. G. Fossum, "Physical insights on nanoscale multi-gate CMOS design," Solid-State Electron., vol. 51, pp. 188-194, Feb. 2007. (Pubitemid 46330454)
19. M. Masahara, R. Surdeanu, L. Witters, G. Doornbos, V. H. Nguyen, G. Van den Bosch, C Vrancken, M. Jurczak, and S. Biesemans, "Experimental investigation of optimum gate workfunction for CMOS four-terminal multigate MOSFETs (MUGFETs)," IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1431-1437, Jun. 2007. (Pubitemid 46864777)
20. A. Tsormpatzoglou, C A. Dimitriadis, R. Clerc, G. Pananakakis, and G. Ghibaudo, "Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 9, pp. 2512-2516, Sep. 2008.
21. S. Tawfik and V. Kursun, "Low-power and robust six-FinFET memory cell using selective gate-drain/source overlap engineering," in Proc Int. Symp. Integr Circuits, 2009, pp. 244-247.
22. S. Tawfik and V. Kursun, "Portfolio of FinFET memories: Innovative techniques for an emerging technology," in Proc ISOCC, Nov. 2008, pp. 101-104.
23. L. Chang, S. Tang, T.-J. King, J. Bokor, and C Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs," in Proc IEDM Tech. Dig., 2000, pp. 719-722. (Pubitemid 32370949)
24. M. Masahara, R. Surdeanu, L. Witters, G. Doornbos, V. H. Nguyen, G. Van den Bosch, C Vrancken, K. Devriendt, F Neuilly, E. Kunnen, M. Jurczak, and S. Biesemans, "Demonstration of asymmetric gate-oxide thickness four-terminal FinFETs having flexible threshold voltage and good subthreshold slope," IEEE Electron Device Lett., vol. 28, no. 3, pp. 217-219, Mar. 2007.
25. A. B. Sachid, C R. Manoj, D. K. Sharma, and V R. Rao, "Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization," IEEE Electron Device Lett., vol. 29, no. 1, pp. 128-130, Jan. 2008.
26. C R. Manoj, M. Nagpal, D. Varghese, and V R. Rao, "Device design and optimization considerations for bulk FinFETs," IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 609-615, Feb. 2008. (Pubitemid 351292051)
27. A. Kuriyama, J. Mitard, O. Faynot, L. Brévard, L. Clerc, A. Tozzo, V Vidal, S. Deleonibus, H. Iwai, and S. Cristoloveanu, "A systematic investigation of work function in advanced metal gate-HfO2-SiO2 structures with bevel oxide," Solid-State Electron., vol. 51, nos. 11-12, pp. 1515-1522, 2007. (Pubitemid 350138032)
28. S. Kim and J. Fossum, "Design optimization and performance projections of double-gate FinFETs with gate-source/drain underlap for SRAM application," IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 1934-1942, Aug. 2007. (Pubitemid 47249825)
29. S. Xiong and J. Bokor, "Sensitivity of double-gate and FinFET devices to process variations," IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2255-2261, Nov. 2003.
30. S. Tawfik and V Kursun, "Low-power and compact sequential circuits with independent-gate FinFETs," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 60-70, Jan. 2008.
31. S. Tawfik and V Kursun, "Multi-threshold voltage FinFET sequential circuits," IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 1, pp. 151-156, Jan. 2011.
32. D. D. Lu, C.-H. Lin, S. Yao, W. Xiong, F Bauer, C R. Cleavelin, A. M. Niknejad, and C Hu, "Design of FinFET SRAM cells using a statistical compact model," in Proc Int. Conf. Simulation Semiconductor Devices Processes, 2009, pp. 1-4.
33. S. Toriyama and N. Sano, "Probability distribution functions of threshold voltage fluctuations due to random impurities in deca-nano MOSFETs," Phys. E: Low-Dimensional Syst. Nanostructures, vol. 19, nos. 1-2, pp. 44-47, Jul. 2003.
34. R. F Sproull and D. Harris, Logical Effort: Designing Fast CMOS Circuits. San Mateo, CA: Morgan Kaufmann, 1999.
35. B. Swahn and S. Hassoun, "Gate sizing: FinFETs versus 32 nm bulk MOSFETs," in Proc Des. Autom. Conf., 2006, pp. 528-531. (Pubitemid 47113954)
36. Abc Synthesis Tools. (2008) [Online]. Available: http://www.eecs. berkeley.edu/alanmi/abc