High-speed low-power finFET based domino logic

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 829-834

  Rasouli, Seid Hadi ^a   Koike, Hanpei ^b   Baneriee, Kaustav ^a  

^a University of California   (United States)

^b NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BACK GATES; CAPACITIVE COUPLINGS; DOMINO LOGIC; EVALUATION PHASE; FINFET DEVICES; GATE VOLTAGES; GATE-SOURCE VOLTAGES; HIGH NOISE; HIGH-SPEED; LOW-POWER; LOWER-POWER CONSUMPTION; RESISTIVE GATES;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; GATES (TRANSISTOR);

FIELD EFFECT TRANSISTORS;

EID: 64549093261     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796583     Document Type: Conference Paper

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