메뉴 건너뛰기




Volumn 28, Issue 3, 2007, Pages 217-219

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

Author keywords

Asymmetric gate oxide thickness; FinFET; four terminal (4T) FinFET; ion bombardment enhanced etching (IBEE); subthreshold slope; threshold voltage control

Indexed keywords


EID: 85008043130     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/LED.2007.891303     Document Type: Article
Times cited : (31)

References (9)
  • 1
    • 1942520273 scopus 로고    scopus 로고
    • High-performance p-type independent-gate FinFET
    • Apr.
    • D. M. Fried, J. S. Duster, and K. T. Kornegay, “High-performance p-type independent-gate FinFET,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 199–201, Apr. 2004.
    • (2004) IEEE Electron Device Lett. , vol.25 , Issue.4 , pp. 199-201
    • Fried, D.M.1    Duster, J.S.2    Kornegay, K.T.3
  • 2
    • 0842288130 scopus 로고    scopus 로고
    • Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel
    • Dec.
    • Y. X. Liu, M. Masahara, K. Ishii, T. Tsutsumi, T. Sekigawa, H. Takashima, H. Yamauchi, and E. Suzuki, “Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel,” in IEDM Tech. Dig., Dec. 2003, pp. 986–988.
    • (2003) IEDM Tech. Dig. , pp. 986-988
    • Liu, Y.X.1    Masahara, M.2    Ishii, K.3    Tsutsumi, T.4    Sekigawa, T.5    Takashima, H.6    Yamauchi, H.7    Suzuki, E.8
  • 3
    • 33745144309 scopus 로고    scopus 로고
    • Multiple independent gate FET (MIGFET)—Multi-Fin RF mixer architecture, three independent gates (MIGFET-T) operation and temperature characteristics
    • Jun.
    • L. Mathew et al., “Multiple independent gate FET (MIGFET)—Multi-Fin RF mixer architecture, three independent gates (MIGFET-T) operation and temperature characteristics,” in VLSI Symp. Tech. Dig., Jun. 2005, pp. 200–201.
    • (2005) VLSI Symp. Tech. Dig. , pp. 200-201
    • Mathew, L.1
  • 4
    • 0020830319 scopus 로고
    • Threshold voltage of thin-film SOI MOSFET's
    • Oct.
    • H. K. Lim and J. G. Fossum, “Threshold voltage of thin-film SOI MOSFET's,” IEEE Trans. Electron Devices, vol. ED-30, no. 10, pp. 1244–1251, Oct. 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , Issue.10 , pp. 1244-1251
    • Lim, H.K.1    Fossum, J.G.2
  • 5
    • 0032284102 scopus 로고    scopus 로고
    • Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
    • Dec.
    • H.-S.P. Wong, D. J. Frank, and P. M. Solomon, “Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation,” in IEDM Tech. Dig., Dec. 1998, pp. 407–410.
    • (1998) IEDM Tech. Dig. , pp. 407-410
    • Wong, H.-S.P.1    Frank, D.J.2    Solomon, P.M.3
  • 6
    • 0035300809 scopus 로고    scopus 로고
    • Novel process for high-density buried nanopyramid array fabrication by means of dopant ion implantation and wet etching
    • no. 4B, pp. Apr.
    • M. Koh, T. Goto, A. Sugita, T. Tanii, T. Iida, T. Shinada, T. Matsukawa, and I. Ohdomari, “Novel process for high-density buried nanopyramid array fabrication by means of dopant ion implantation and wet etching,” Jpn. J. Appl. Phys., vol. 40, no. 4B, pp. 2837–2839, Apr. 2001.
    • (2001) Jpn. J. Appl. Phys. , vol.40 , pp. 2837-2839
    • Koh, M.1    Goto, T.2    Sugita, A.3    Tanii, T.4    Iida, T.5    Shinada, T.6    Matsukawa, T.7    Ohdomari, I.8
  • 8
    • 33745139143 scopus 로고    scopus 로고
    • Tall triple-gate devices with TiN/Hf02 gate stack
    • Jun.
    • N. Collaert et al., “Tall triple-gate devices with TiN/Hf02 gate stack,” in VLSI Symp. Tech. Dig., Jun. 2005, pp. 108–109.
    • (2005) VLSI Symp. Tech. Dig. , pp. 108-109
    • Collaert, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.