Design of FinFET SRAM cells using a statistical compact model

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2009, Pages

  Lu, Darsen D ^a   Lin, Chung Hsun ^a   Yao, Shijing ^a   Xiong, Weize ^b   Bauer, Florian ^c,d,e   Cleavelin, Cloves R ^b   Niknejad, Ali M ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c INFINEON TECHNOLOGIES AG   (Germany)

^d TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^e 205 Cory Hall 1722 ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL DESIGN; COMPACT MODEL; ELECTRICAL MEASUREMENT; FIN WIDTHS; GATE LENGTH; MONTE CARLO; P-TYPE; SOI FINFETS; SRAM CELL; STATIC LEAKAGE; STATISTICAL SIMULATION;

SEMICONDUCTOR DEVICES; STATIC RANDOM ACCESS STORAGE;

FIELD EFFECT TRANSISTORS;

EID: 74349127359     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2009.5290234     Document Type: Conference Paper

References (7)

1. X. Huang et al., "Sub 50-nm FinFET: PMOS," IEDM Tech. Dig., pp. 67-70, 1999.
2. H. Kawasaki et al., "Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond," VLSI Symp. Tech. Dig., pp. 70-71, 2006.
3. Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King and B. Nikolic, "FinFET-Based SRAM Design," ISLPED, pp. 2-7, 2005.
4. M. V. Dunga et al, "BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design," VLSI Symp. Tech. Dig., pp. 60-61, 2007.
5. F. Bauer et al., "Layout Options for Stability Tuning of SRAM Cells in Multi-Gate-FET Technologies," ESSCIRC, pp. 392-395, 2007.
6. Y. Cheng and C. Hu, MOSFET Modeling and BSIM3 User's Guide, Springer, 1999.
7. H. Yamauchi, Variation-Tolerant SRAM Circuit Designs, ISSCC Tutorial, 2009.