Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization

IEEE Electron Device Letters

Volumn 29, Issue 1, 2008, Pages 128-130

  Sachid, Angada B ^a   Manoj, C R ^a   Sharma, Dinesh K ^a   Rao, V Ramgopal ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

CMOS scaling; FinFET; Fringe induced barrier lowering (GFIBL); High materials; Short channel effects (SCEs)

Indexed keywords

CMOS INTEGRATED CIRCUITS; OPTIMIZATION; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

GATE FRINGE-INDUCED BARRIER LOWERING (GFIBL); SHORT-CHANNEL EFFECTS (SCES);

GATES (TRANSISTOR);

EID: 37549024549     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.911974     Document Type: Article

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