First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Wu, Y Q ^a   Wang, R S ^a   Shen, T ^a   Gu, J J ^a   Ye, P D ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D STRUCTURE; DAMAGE-FREE; ELEVATED TEMPERATURE; ETCHING METHOD; FINFETS; GATE LENGTH; MOSFETS; SHORT-CHANNEL EFFECT; STATIC CONTROL;

ELECTRON DEVICES; ETCHING; GATE DIELECTRICS; GATES (TRANSISTOR); MOSFET DEVICES;

SEMICONDUCTING INDIUM;

EID: 77952417120     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424356     Document Type: Conference Paper

References (10)

1. Y. Xuan et al., IEEE Electron Device Lett., 29, 294 (2008).
2. T.D. Lin et al. Applied Physics Letters 93, 033516 (2008).
3. N. Goel et al., IEDM Tech. Dig. 363 (2008).
4. Y. Sun et al., IEDM Tech. Dig. 367 (2008).
5. Y.Q. Wu et al., IEEE Electron Device Lett., 30, 700 (2009).
6. D. Hisamoto et al., IEEE Trans. Electron Device, 47, 2320 (2000).
7. H.-S.P Wong, IBM J. Res. & Dev. 46, 133 (2002).
8. B.S. Doyle et al., IEEE Electron Device Lett., 24, 263 (2003).
9. A. Veloso et al., IEDM Tech. Dig. 861 (2008).
10. J.-W. Yang et al., VLSI Tech. Dig. 20 (2008).