Device design and optimization considerations for bulk FinFETs

IEEE Transactions on Electron Devices

Volumn 55, Issue 2, 2008, Pages 609-615

  Manoj, C R ^a   Nagpal, Meenakshi ^a   Varghese, Dhanya ^a   Rao, V Ramgopal ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Bulk FinFET; Device parasitics; Fringe capacitance; Inverter delay; SOI FinFET

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY;

BULK FIN FIELD EFFECT TRANSISTOR; FRINGE CAPACITANCE;

FIELD EFFECT TRANSISTORS;

EID: 39749142331     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.912996     Document Type: Article

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