Dual-k spacer device architecture for the improvement of performance of silicon n-channel tunnel FETs

IEEE Transactions on Electron Devices

Volumn 57, Issue 10, 2010, Pages 2410-2417

  Virani, Hasanali G ^a,b   Adari, Rama Bhadra Rao ^a   Kottantharayil, Anil ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b GOA COLLEGE OF ENGINEERING   (India)

Author keywords

Band to band tunneling; high k; subthreshold slope; tunnel field effect transistor

Indexed keywords

BAND TO BAND TUNNELING; DEVICE ARCHITECTURES; DEVICE SIMULATIONS; HIGH-K; HIGH-K MATERIALS; INNER LAYER; LOW-K MATERIALS; N-CHANNEL; OFF-STATE CURRENT; ON STATE CURRENT; OUTER LAYER; PERFORMANCE IMPROVEMENTS; SUBTHRESHOLD SLOPE; TUNNEL FET; TUNNELING FET;

GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; MESFET DEVICES; SILICON COMPOUNDS; SILICON OXIDES;

FIELD EFFECT TRANSISTORS;

EID: 77956986294     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2057195     Document Type: Article

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