High-performance and low-power bulk logic platform utilizing FET specific multiple-stressors with highly enhanced strain and full-porous low-k interconnects for 45-nm CMOS technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 251-254

  Miyashita, T ^a   Ikeda, K ^a   Kim, Y S ^a   Yamamoto, T ^a   Sambonsugi, Y ^a   Ochimizu, H ^a   Sakoda, T ^a   Okuno, M ^a   Minakata, H ^a   Ohta, H ^a   Hayami, Y ^a   Ookoshi, K ^a   Shimamune, Y ^a   Fukuda, M ^a   Hatada, A ^a   Okabe, K ^a   Kubo, T ^a   Tajima, M ^a   Motoh, E ^a   Owada, T ^a   Nakamura, M ^a   Kudo, H ^a   Sawada, T ^a   Nagayama, J ^a   Satoh, A ^a   Mori, T ^a   Hasegawa, A ^a   Kurata, H ^a   Sukegawa, K ^a   Tsukune, A ^a   Yamaguchi, S ^a   Kase, M ^a   Futatsugi, T ^a   Satoh, S ^a   Sugii, T ^a   more..

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; MESFET DEVICES; TECHNOLOGY;

BULK CMOS; CMOS TECHNOLOGIES; DRIVE CURRENTS; END USES; LOW POWERS; MULTI CORES; OFF CURRENTS; PLATFORM TECHNOLOGY; POROUS LOW-K;

FIELD EFFECT TRANSISTORS;

EID: 50249091603     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418915     Document Type: Conference Paper

References (7)

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7. H. Kudo et al., Proc. IITC, p.178, 2007.