A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 208-209

  Park, C S ^a   Hussain, M M ^a   Huang, J ^a   Park, C ^a   Tateiwa, K ^a   Young, C ^a   Park, H K ^a   Cruz, M ^a   Gilmer, D ^a   Rader, K ^a   Price, J ^a   Lysaght, P ^a   Heh, D ^a   Bersuker, G ^a   Kirsch, P D ^a   Tseng, H H ^a   Jammy, R ^a  

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

32 NM TECHNOLOGY; CAP REMOVAL; CMOS INTEGRATION; CMOS TRANSISTORS; METAL GATE MATERIALS; OVERLAY TOLERANCES; SINGLE CHANNELS;

HAFNIUM COMPOUNDS; SILICON COMPOUNDS;

METAL RECOVERY;

EID: 71049170548     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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11. International Technology Roadmap for Semiconductors, 2008 update.