Is overlay error more important than interconnect variations in double patterning?

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2009, Pages 3-10

  Jeong, Kwangok ^a   Kahng, Andrew B ^a   Topaloglu, Rasit O ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Double patterning lithography; Interconnect variations; Overlay

Indexed keywords

CHIP-LEVEL; DOUBLE PATTERNING; DOUBLE PATTERNING LITHOGRAPHY; INTERCONNECT COUPLING CAPACITANCE; INTERCONNECT LAYERS; OVERLAY ERRORS; PERFORMANCE IMPACT; PERFORMANCE VARIATIONS;

ELECTRIC POWER SYSTEM INTERCONNECTION; INFRARED DETECTORS; TECHNICAL PRESENTATIONS;

LITHOGRAPHY;

EID: 77950164684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1572471.1572474     Document Type: Conference Paper

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