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Volumn 2006, Issue , 2006, Pages 29-34

Generation of design guarantees for interconnect matching

Author keywords

Design guarantee generation; DFM; Interconnect matching

Indexed keywords

COMPUTER SIMULATION; FEATURE EXTRACTION; MATHEMATICAL MODELS; MONTE CARLO METHODS; OPTIMIZATION; PARAMETER ESTIMATION; PATTERN MATCHING;

EID: 33750923113     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/1117278.1117285     Document Type: Conference Paper
Times cited : (9)

References (12)
  • 1
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    • p. Section 10C.4
    • M. R. Becer et al., "Pessimism reduction in crosstalk noise aware sta," in Proceedings of ICCAD 2005, 2005, p. Section 10C.4.
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  • 2
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    • Reducing pessimism in rlc delay estimation using an accurate analytical frequency dependent model for inductance
    • p. Section 8A.3
    • M. Mondal and Y. Massoud, "Reducing pessimism in rlc delay estimation using an accurate analytical frequency dependent model for inductance," in Proceedings of ICCAD 2005, 2005, p. Section 8A.3.
    • (2005) Proceedings of ICCAD 2005
    • Mondal, M.1    Massoud, Y.2
  • 4
    • 0037346346 scopus 로고    scopus 로고
    • Understanding mosfet mismatch for analog design
    • Mar.
    • P. G. Drennan and C. C. McAndrew, "Understanding mosfet mismatch for analog design," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 450-456, Mar. 2003.
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    • Drennan, P.G.1    McAndrew, C.C.2
  • 6
    • 84886448086 scopus 로고    scopus 로고
    • Modeling of pattern-dependent on-chip interconnect geometry variation for deep-submicron process and design technology
    • O. Nakagawa, S.-Y. Oh, and G. Ray, "Modeling of pattern-dependent on-chip interconnect geometry variation for deep-submicron process and design technology," in Technical Digest of International Electron Devices Meeting, 1997, pp. 137-140.
    • (1997) Technical Digest of International Electron Devices Meeting , pp. 137-140
    • Nakagawa, O.1    Oh, S.-Y.2    Ray, G.3
  • 7
    • 0034276317 scopus 로고    scopus 로고
    • Tradeoff between interconnect capacitance and re delay variations induced by process fluctuations
    • Sept
    • N. Shigyo, "Tradeoff between interconnect capacitance and re delay variations induced by process fluctuations," IEEE Transactions on Electron Devices, vol. 47, no. 9, pp. 1740-1744, Sept, 2000.
    • (2000) IEEE Transactions on Electron Devices , vol.47 , Issue.9 , pp. 1740-1744
    • Shigyo, N.1
  • 8
    • 2942576140 scopus 로고    scopus 로고
    • Rapid method to account for process variation in full-chip capacitance extraction
    • Dec.
    • A. Labun, "Rapid method to account for process variation in full-chip capacitance extraction," IEEE Journal of CAD, vol. 23, no. 12, pp. 1677-1683, Dec. 2004,
    • (2004) IEEE Journal of CAD , vol.23 , Issue.12 , pp. 1677-1683
    • Labun, A.1
  • 9
    • 0032204374 scopus 로고    scopus 로고
    • Circuit sensitivity to interconnect variation
    • Nov.
    • Z. Lin, C. Spanos, L. Milor, and Y. Lin, "Circuit sensitivity to interconnect variation," IEEE Trans. Semiconduct. Manufact., vol. 11, no. 4, pp. 557-568, Nov. 1998.
    • (1998) IEEE Trans. Semiconduct. Manufact. , vol.11 , Issue.4 , pp. 557-568
    • Lin, Z.1    Spanos, C.2    Milor, L.3    Lin, Y.4
  • 12
    • 27944490407 scopus 로고    scopus 로고
    • Impact of process variations on multi-level signaling for on-chip interconnects
    • V. Venkatraman and W. Burleson, "Impact of process variations on multi-level signaling for on-chip interconnects," in 18th International Conference on VLSI Design, 2005, pp. 362-367.
    • (2005) 18th International Conference on VLSI Design , pp. 362-367
    • Venkatraman, V.1    Burleson, W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.