Design-overlay interactions in metal double patterning

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7275, Issue , 2009, Pages

  Ghaida, Rani S ^a   Gupta, Puneet ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Alignment strategy; Congestion; DFM; Double patterning; Overlay; Overlay budget; Overlay control; Wire spreading; Wire widening

Indexed keywords

CONGESTION; DFM; DOUBLE PATTERNING; OVERLAY; OVERLAY BUDGET; OVERLAY CONTROL;

ALIGNMENT; CAPACITANCE; MACHINE DESIGN; WIRE;

BUDGET CONTROL;

EID: 66749159884     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.814299     Document Type: Conference Paper

References (15)

1. International Technology Roadmap for Semiconductors, report, (2007).
2. C. A. Mack, "Seeing double," IEEE Spectrum, pp. 46-51, Nov. 2008.
3. W. Arnold, M. Dusa, and J. Finders, "Manufacturing challenges in double patterning lithography," IEEE Intl. Symp. Semiconductor Manufacturing , pp.283-286, 25-27 Sept. 2006.
4. C. Lim et. al., "Positive and negative tone double patterning lithography for 50nm flash memory," SPIE Optical Microlithography XIX, pp. 615410-1 - 615410-8, (2006).
5. D. Laidler, P. Leray, K. Dhav, and S. Cheng "Sources of Overlay Error in Double Patterning Integration Schemes," SPIE Metrology, Inspection, and Process Control for Microlithography XXII, 69221, 69221E, (2008).
6. R. Kim, T. Wallow, J. Kye, H. J. Levinson, and D. White,"Double exposure using 193nm negative tone photoresist," Proc. SPIE Optical Microlithography XX, 6520, 65202M (2007).
7. C. Chien and K. Chang, "Modeling overlay errors and sampling strategies to improve yield," Journal of the Chinese Institute of Industrial Engineers, vol. 18, no. 3, pp. 95-103 (2001).
8. W. H. Arnold, "Towards 3nm overlay and critical dimension uniformity: an integrated error budget for double patterning lithography," Proc. SPIE Optical Microlithography XXI, 6924, 692404 (2008).
9. M. Dusa et. al., "Pitch doubling through dual patterning lithography challenges in integration and litho budgets," Proc. SPIE Optical Microlithography XX, 6520, 65200G, (2007).
10. B. Eichelberger et. al., "32nm overlay improvement capabilities," Proc. SPIE Optical Microlithography XXI, 6924, 69244C (2008).
11. S. Wakamoto et. al., "Improved overlay control through automated high-order compensation," SPIE Metrology, Inspection, and Process Control for Microlithography XXI, 6518, 65180J, (2007).
12. H. J. Levinson, Principles of Lithography, SPIE-International Society for Optical Engineering, 2nd ed., Bellingham, WA, pp. 213-220, (2004).
13. U. Iessi et. al.,"Double Patterning Overlay and CD budget for 32 nm technology node," SPIE Optical Microlithography XXI, 6924, 692428, (2008).
14. L. Lecarpentier et. al., "Overlay measurement accuracy verification using CD-SEM and application to the quantification of WIS caused by BARC," SPIE Metrology, Inspection, and Process Control for Microlithography XIX, 5752(1), pp. 1413-1423, (2005).
15. A. J. Hazelton et. al., "Double patterning requirements for optical lithography and prospects for optical extension without double patterning," SPIE Optical Microlithography XXI, 6924, 69240R, (2008).