Statistical and corner modeling of interconnect resistance and capacitance

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 853-856

  Lu, Ning ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC RESISTANCE; MONTE CARLO METHODS; NANOELECTRONICS; SPICE;

INTERCONNECT CORNER MODELS; INTERCONNECT SPICE MODEL;

INTERCONNECTION NETWORKS;

EID: 34748905251     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320845     Document Type: Conference Paper

References (10)

1. C. Goldberg, et al., Proc. 2005 IITC, pp. 3-5, June 2005.
2. M. Fukasawa, et al., Proc. 2005 IITC, pp. 9-11, June 2005.
3. J. Farcy, et al., Proc. 2005 IITC, pp. 74-76, June 2005.
4. N. Nsgaraj, et al., Proc. 2005 IITC, pp. 71-73, June 2005.
5. N. Lu, M. Tong, and E. Conrad, "IBM interconnect modeling," IBM MicroNews, Vol. 5, No. 4, pp. 22-25, 1999.
6. Efficient Rapid Integrated Extraction (ERIE) program User's Manual, IBM Corporation.
7. E. Leobandung, et al., in Proc. Symposium on VLSI Technology, 2005, pp. 126-127.
8. A. Dharchoudhury et al., IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, pp. 481-492, 1995.
9. M. Sengupta, et al., IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, pp. 1372-1380, 2005.
10. A. A. Mutlu and M Rahman, IEEE Trans. Electronics Packaging Manufacturing, Vol. 28, pp. 364-374, 2005.