Development of 38nm bit-lines using copper damascene process for 64-giga bits NAND flash

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn , Issue , 2008, Pages 49-51

  Hwang, Byungjoon ^a   Lim, Namsu ^a   Park, Jang Ho ^a   Jin, Sowi ^a   Kim, Minjeong ^a   Jung, Jaesuk ^a   Kwon, Byungho ^a   Hong, Jongwon ^a   Han, Jeehoon ^a   Kwak, Donghwa ^a   Park, Jaekwan ^a   Choi, Jung Dai ^a   Lee, Won Seong ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COPPER; ELECTRIC CONDUCTIVITY; ELECTRIC RESISTANCE; HETEROJUNCTION BIPOLAR TRANSISTORS; SEMICONDUCTOR MATERIALS; SHEET RESISTANCE; STATIC RANDOM ACCESS STORAGE;

BIT-LINES; COPPER DAMASCENE PROCESS; DOUBLE PATTERNING; HIGH-DENSITY; LOW-PARASITIC; NAND FLASH; NODE TECHNOLOGY; PARASITIC CAPACITANCES; SELF-ALIGNED; SEMICONDUCTOR MANUFACTURING;

CMOS INTEGRATED CIRCUITS;

EID: 49149096604     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2008.4529005     Document Type: Conference Paper

References (5)

1. Kinam Kim et al., "Future Outlook of NAND Flash Technology for 40nm Node and Beyond", IEEE NVSMW, pp. 9-11, 2006.
2. Jung-Dai Choi et al., "A 0.15 um NAND Flash Technology with 0.11um2 Cell Size for 1 Gbit Flash Memory", IEDM, pp. 767-770, 2000.
3. Byungjoon Hwang et al "Comparison of SADP vs. RSADP using Off-set spacer for Bit-line contacts of 76nm pitch on NAND Flash cell", ICMTD2007
4. Byungjoon Hwang et al, "Modeling of Re-sputtering induced Bridge of Tungsten Bit-Lines for NAND Flash Memory Cell with 37nm node Technology", SISPAD2007
5. Byungjoon Hwang et al, "Development of Bit-Line Contact of 76nm pitch on NAND Flash Cell using Reversal PR and SADP Process", ASMC, pp. 356-358, 2007