Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations

IEEE Transactions on Electron Devices

Volumn 47, Issue 9, 2000, Pages 1740-1744

  Shigyo, Naoyuki ^a,b  

^a IEEE   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER INTERCONNECT; CRITICAL DIMENSION VARIATION; FRINGING CAPACITANCE; INTERCONNECT CAPACITANCE; INTERCONNECT DESIGN GUIDELINE; PROCESS FLUCTUATION;

APPROXIMATION THEORY; COMPUTER SIMULATION; COPPER; CURVE FITTING; ELECTRIC CONDUCTIVITY OF SOLIDS; ELECTRIC FIELDS; PERMITTIVITY; SILICON COMPOUNDS;

CAPACITANCE;

EID: 0034276317     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.861585     Document Type: Article

References (10)

1. S. W. Director and W. Maly, Eds., Statistical Approach to VLSI. Amsterdam, The Netherlands: North-Holland, 1994.
2. D. M. H. Walker et al., "A TCAD framework for development and manufacturing," in Technology CAD Systems, F. Fashing etal., Eds., 1993, p. 83.
3. N. Shigyo et al., "Technology CAD based statistical simulation of MOSFET's," Solid-State Electron., vol. 44, p. 1001, 2000.
4. R. L. M. Dang and N. Shigyo, "Coupling capacitance for two-dimensional wires," IEEE Electron Device Lett., vol. EDL-2, p. 196, 1981.
5. M. T. Bohr, "Interconnect scaling-The real limiter to high performance ULSI," in IEDM Tech. Dig., p. 241.
6. O. S. Nakagawa et al, "Circuit impact and skew-corner analysis of stochastic process variation in global interconnect," in Proc. Int. Interconnect Tech. Conf., 1999, p. 230.
7. M. Orshansky et al, "Circuit performance variability decomposition," in Proc. 1999IWSM, p. 10.
8. N. Shigyo, S. Fukuda, and K. Kato, "The influence of boundary locations on wiring capacitance simulation," IEEE Trans. Electron Devices, vol. ED-36, p. 1171, 1989.
9. T. Sakurai, "Closed-form expressions for interconnect delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol.40, p. 118, 1993.
10. H. B. Bakoglu and J. D. Meindl, "Optimum interconnection circuits for VLSI," IEEE Trans. Electron Devices, vol. ED-32, p. 903, 1985.