Rapid method to account for process variation in full-chip capacitance extraction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 6, 2004, Pages 941-951

  Labun, Andrew ^a,b  

^a HEWLETT PACKARD COMPANY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Capacitance; Design for manufacturability; Integrated circuit interconnections; Integrated circuit layout; Process variation; Sensitivity

Indexed keywords

DESIGN FOR MANUFACTURABILITY; INTEGRATED CIRCUIT INTERCONNECTIONS; PROCESS VARIATION; SENSITIVITY;

CAPACITANCE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; COMPUTER SOFTWARE; EXTRAPOLATION; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PERTURBATION TECHNIQUES; RANDOM PROCESSES; RELIABILITY; SIMULATORS; STATISTICS;

VLSI CIRCUITS;

EID: 2942576140     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.828111     Document Type: Article

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