Impact of process variations on multi-level signaling for on-chip interconnects

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 362-367

  Venkatraman, Vishak ^a   Burleson, Wayne ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTI-LEVEL SIGNALING; ON-CHIP DESIGNS; PROCESS VARIATIONS;

INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; SENSITIVITY ANALYSIS; THRESHOLD VOLTAGE;

SIGNAL PROCESSING;

EID: 27944490407     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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