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Volumn 54, Issue 2, 2010, Pages 213-219

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

Author keywords

Short channel effect; SOI MOSFET; Substrate coupling; Subthreshold slope; Thin BOX; UTB

Indexed keywords

ANALYTICAL MODELING; ATLAS SIMULATIONS; BURIED OXIDES; CHANNEL POSITION; COMPREHENSIVE STUDIES; ELECTRICAL PARAMETER; GATE LENGTH; SHORT-CHANNEL EFFECT; SOI-MOSFETS; SPACE CHARGES; SUBSTRATE BIAS; SUBSTRATE COUPLINGS; SUBTHRESHOLD SLOPE; ULTRA-THIN; ULTRATHIN BODY; UNDOPED CHANNELS;

EID: 76349087827     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.12.021     Document Type: Article
Times cited : (46)

References (35)
  • 2
    • 2342583496 scopus 로고    scopus 로고
    • Controlling short-channel in deep-submicron SOI MOSFET's for improved reliability: a review
    • Chaudhry A., Chaudhry A., and Kumar M. Controlling short-channel in deep-submicron SOI MOSFET's for improved reliability: a review. IEEE Trans Dev Mater Reliab (2004) 99-109
    • (2004) IEEE Trans Dev Mater Reliab , pp. 99-109
    • Chaudhry, A.1    Chaudhry, A.2    Kumar, M.3
  • 3
    • 12444292832 scopus 로고    scopus 로고
    • Nanoscale FD/SOI CMOS: thick or thin BOX?
    • Trivedi V., and Fossum J. Nanoscale FD/SOI CMOS: thick or thin BOX?. IEEE Electron Dev Lett 26 (2005) 26-28
    • (2005) IEEE Electron Dev Lett , vol.26 , pp. 26-28
    • Trivedi, V.1    Fossum, J.2
  • 4
    • 25844508965 scopus 로고    scopus 로고
    • Integration of buried insulators with high thermal conductivity in SOI MOSFET's: thermal properties and short channel effects
    • Bresson N., Cristoloveanu S., Mazuré C., Letertre F., and Iwai H. Integration of buried insulators with high thermal conductivity in SOI MOSFET's: thermal properties and short channel effects. Solid State Electron 49 (2005) 1522-1528
    • (2005) Solid State Electron , vol.49 , pp. 1522-1528
    • Bresson, N.1    Cristoloveanu, S.2    Mazuré, C.3    Letertre, F.4    Iwai, H.5
  • 7
    • 34547781729 scopus 로고    scopus 로고
    • Impact of parameter variations and random dopant fluctuations on short-channel fully depleted SOI MOSFET's with extremely thin BOX
    • Ohtou T., Sugii N., and Hiramoto T. Impact of parameter variations and random dopant fluctuations on short-channel fully depleted SOI MOSFET's with extremely thin BOX. IEEE Electron Dev Lett 28 (2007) 740-742
    • (2007) IEEE Electron Dev Lett , vol.28 , pp. 740-742
    • Ohtou, T.1    Sugii, N.2    Hiramoto, T.3
  • 10
    • 0036498428 scopus 로고    scopus 로고
    • Fringing fields in sub-0.1 μm fully depleted SOI MOSFET's: optimization of the device architecture
    • Ernst T., Tinella C., Raynaud C., and Cristoloveanu S. Fringing fields in sub-0.1 μm fully depleted SOI MOSFET's: optimization of the device architecture. Solid State Electron 46 (2002) 373-378
    • (2002) Solid State Electron , vol.46 , pp. 373-378
    • Ernst, T.1    Tinella, C.2    Raynaud, C.3    Cristoloveanu, S.4
  • 15
    • 21644447069 scopus 로고    scopus 로고
    • Silicon on thin BOX: A new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control
    • Horiuchi M, editor, IEEE international;
    • Tsuchiya R, Tsuchiya R, Horiuchi M, Kimura S, Yamaoka M, Kawahara T, et al. Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control. In: Horiuchi M, editor. Proceedings of the IEDM technical digest electron devices meeting IEEE international; 2004. p. 631-4.
    • (2004) Proceedings of the IEDM technical digest electron devices meeting , pp. 631-634
    • Tsuchiya, R.1    Tsuchiya, R.2    Horiuchi, M.3    Kimura, S.4    Yamaoka, M.5    Kawahara, T.6
  • 16
    • 33847333096 scopus 로고    scopus 로고
    • Ultra-thin fully-depleted SOI MOSFET's: special charge properties and coupling effects
    • Eminente S., Cristoloveanu S., Clerc R., Ohata A., and Ghibaudo G. Ultra-thin fully-depleted SOI MOSFET's: special charge properties and coupling effects. Solid State Electron 51 (2007) 239-244
    • (2007) Solid State Electron , vol.51 , pp. 239-244
    • Eminente, S.1    Cristoloveanu, S.2    Clerc, R.3    Ohata, A.4    Ghibaudo, G.5
  • 18
    • 76349108896 scopus 로고    scopus 로고
    • Boeuf F, Skotnicki T, Monfray S, Julien C, Dutartre D, Martins J, et al. 16 nm planar nMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation. In: Proceedings of the IEDM technical digest electron devices meeting international; 2001. p. 29.5.1-4.
    • Boeuf F, Skotnicki T, Monfray S, Julien C, Dutartre D, Martins J, et al. 16 nm planar nMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation. In: Proceedings of the IEDM technical digest electron devices meeting international; 2001. p. 29.5.1-4.
  • 22
    • 47749102120 scopus 로고    scopus 로고
    • Armstrong, 6-T SRAM cell design with nanoscale double-gate SOI MOSFET's: impact of source/drain engineering and circuit topology
    • Rashmi A., and Kranti G.A. Armstrong, 6-T SRAM cell design with nanoscale double-gate SOI MOSFET's: impact of source/drain engineering and circuit topology. Semicond Sci Technol 075049 (2008) 23-35
    • (2008) Semicond Sci Technol , vol.075049 , pp. 23-35
    • Rashmi, A.1    Kranti, G.A.2
  • 27
    • 0026366830 scopus 로고
    • Measurement of threshold voltages of thin film accumulation-mode PMOS/SOI transistors
    • Terao A., Flandre D., Lora-Tamayo E., and Van de Wiele F. Measurement of threshold voltages of thin film accumulation-mode PMOS/SOI transistors. IEEE Electron Dev Lett 12 (1991) 682-684
    • (1991) IEEE Electron Dev Lett , vol.12 , pp. 682-684
    • Terao, A.1    Flandre, D.2    Lora-Tamayo, E.3    Van de Wiele, F.4
  • 28
    • 0020830319 scopus 로고
    • Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's
    • Lim H.-K., and Fossum J. Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's. IEEE Trans Electron Dev 30 (1983) 1244-1251
    • (1983) IEEE Trans Electron Dev , vol.30 , pp. 1244-1251
    • Lim, H.-K.1    Fossum, J.2
  • 29
    • 0030865493 scopus 로고    scopus 로고
    • Substrate influences on fully depleted enhancement mode SOI MOSFET's at room temperature and at 77 K
    • Pavanello M.A., Martino J.A., and Colinge J.-P. Substrate influences on fully depleted enhancement mode SOI MOSFET's at room temperature and at 77 K. Solid State Electron 41 (1997) 111-119
    • (1997) Solid State Electron , vol.41 , pp. 111-119
    • Pavanello, M.A.1    Martino, J.A.2    Colinge, J.-P.3
  • 30
    • 0025468856 scopus 로고
    • Model for the potential drop in the silicon substrate for thin-film SOI MOSFET's
    • Martino J., Lauwers L., Colinge J., and De Meyer K. Model for the potential drop in the silicon substrate for thin-film SOI MOSFET's. Electron Lett 26 (1990) 1462-1464
    • (1990) Electron Lett , vol.26 , pp. 1462-1464
    • Martino, J.1    Lauwers, L.2    Colinge, J.3    De Meyer, K.4
  • 32
    • 0029379215 scopus 로고
    • Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology
    • Yeh P.C., and Fossum J. Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology. IEEE Trans Electron Dev 42 (1995) 1605-1613
    • (1995) IEEE Trans Electron Dev , vol.42 , pp. 1605-1613
    • Yeh, P.C.1    Fossum, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.