Requirements for ultra-thin-film devices and new materials for the CMOS roadmap

Solid-State Electronics

Volumn 48, Issue 6, 2004, Pages 961-967

  Fenouillet Beranger, C ^b   Skotnicki, T ^a   Monfray, S ^a   Carriere, N ^b   Boeuf, F ^a  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

Author keywords

BOX; DIBL; Fully depleted; Metal gates; Short channel effects; SOI; Strained silicon; Subthreshold slope

Indexed keywords

POLYSILICON; QUANTUM THEORY; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; ULTRATHIN FILMS;

BOX; DIBL; FULLY-DEPLETED; METAL GATES; SHORT-CHANNEL EFFECTS; STRAINED SILICON; SUBTHRESHOLD SLOPE;

CMOS INTEGRATED CIRCUITS;

EID: 1442311898     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.12.039     Document Type: Article

References (28)

1. International Technology Roadmap for Semiconductors. 2001;Semiconductor Industry Association, San Jose, CA.
2. Chen K., et al. The impact of device scaling and power supply change on CMOS gate performances. IEEE Electron Device Lett. (May):1996;202-204.
3. Skotnicki T, et al. IEEE Trans. Electron Devices (in press).
4. Skotnicki T, et al. A New Analog/Digital CAD Model for Sub-halfmicron MOSFETs. IEDM Technical Digest, 1994. p. 165-8.
5. Skotnicki T. Analysis of the Silicon Technology Roadmap - How far can CMOS go? T1, Series IV:2000;885-909 Academie des Sciences Paris, Paris.
6. Uchida K, et al. Experimental Study on Carrier Transport Mechanism in Ultrathin-body SOI n and p MOSFETs with SOI Thickness less than 5 nm. IEDM Technical Digest, 2002. p. 47-50.
7. Ren Z, et al. Examination of Hole Mobility in Ultra-thin Body SOI MOSFETs. IEDM Technical Digest, 2002. p. 51-4.
8. Monfray S, et al. SON (Silicon On Nothing) P-MOSFETs with totally silicided (CoSi) Polysilicon on 5 nm thick Si films: The simplest way to integration of metal gates on thin FD channels. IEDM Technical Digest, 2002. p. 263-66.
9. Skotnicki T. Heading for decananometer CMOS - Is navigation among icebergs still a viable strategy? Proceedings of ESSDERC, 2000. p. 19-33.
10. Skotnicki T, et al. Physique des dispositifs pour circuits intégrés silicium Sous la direction de J. Gautier, Hermes Science, EGEM 2003.
11. Thompson S, et al. An Enhanced 130 nm Generation Logic Technology Featuring 60 nm Transistors Optimized for High Performance and Low Power at 0.7-1.4 V. IEDM Technical Digest, 2001. p. 257-61.
12. Takao V, et al. 0.65 V Device Design with High-performance and High density 100 nm CMOS Technology for Low Operation Power Application Symposium on VLSI Technology, 2002. p. 122-23.
13. Schafbauer T, et al. Integration of High performance, Low leakage and Mixed Signal Features into a 100 nm CMOS Technology. Symposium on VLSI Technology, 2002. p. 62-3.
14. Fukasaku K, et al. UX6-100 nm Generation CMOS Integration Technology with Cu/Low- k Interconnect. Symposium on VLSI Technology, 2002. p. 64-5.
15. Yeap GC-F, et al. A 100 nm Copper/Low-K Bulk CMOS Technology with Multi Vt and Multi Gate Oxide Integrated Transistors for Low Standby Power, High Performance and RF/Analog System on Chip Applications. Symposium on VLSI Technology, 2002. p. 16-7.
16. Huang S-F, et al. High Performance 50 nm CMOS Devices for Microprocessor and Embedded Processor Core Applications. IEDM Technical Digest, 2001. p. 237-40.
17. Nakai S, et al. A 100 nm CMOS Technology with Sidewall Notched 40nm Transistors and SiC Capped Cu/VLK Interconnects for High Performance Microprocessor Applications. Symposium on VLSI Technology, 2002. p. 66-7.
18. Mehrotra M, et al. 60 nm Gate Length Dual Vt CMOS for High Performance Applications. Symposium on VLSI Technology, 2002. p. 124-5.
19. Parihar S, et al. A High Density 0.10 μ m CMOS Technology Using Low K Dielectric and Copper Interconnect. IEDM Technical Digest, 2001. p. 249-52.
20. Rim K, et al. Mobility Enhancement in Strained Si NMOSFETs with HfO2 Gate Dielectrics. Symposium on VLSI Technology, 2002. p. 12-3.
21. Wong H-SP, et al. Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-thin SOI MOSFET's at the 25 nm Channel Length Generation. IEDM Technical Digest, 1998. p. 407-10.
22. Luyken RJ, et al. Perspectives of Fully-depleted SOI transistors down to 20 nm gate length. IEEE International SOI conference, 2002. p. 137-39.
23. Vandooren A, et al. Scaling Assessment of Fully-Depleted SOI Technology At the 30 nm Gate Length Generation IEEE International SOI conference, 2002. p. 25-7.
24. Su L.T., et al. Deep submicrometer channel design in silicon on Insulator (SOI) MOSFET's. IEEE Electron Device Lett. 1994;366-369.
25. Koh R. Buried layer engineering to reduce the drain induced barrier lowering of sub-0.05 μm SOI MOSFET. Jpn. J. Appl. Phys. 38:1999;2294-2299.
26. Jurczak M., et al. Silicon on nothing (SON) an innovative process for advanced CMOS. IEEE Trans. Electron Devices. (Nov):2000;2179-2187.
27. Ernst T., et al. Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture. Solid State Electron. 46:2002;373-378.
28. Josse E, et al. Polysilicon gate with depletion or metallic gate with buried channel: what evil worse. IEDM Technical Digest, 1999. p. 661-4.