Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: Optimization of the device architecture

Solid-State Electronics

Volumn 46, Issue 3, 2002, Pages 373-378

  Ernst, T ^a,b   Tinella, C ^a   Raynaud, C ^c   Cristoloveanu, S ^a  

^a Grenoble INP Phelma   (France)

^b STMICROELECTRONICS   (France)

^c CEA LETI   (France)

Author keywords

DIBL; Fringing field; Full depletion; MOSFET; Short channel effects; SOI

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); OPTIMIZATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; ULTRATHIN FILMS;

SHORT-CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0036498428     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(01)00111-3     Document Type: Article

References (9)

1. Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology
2. Two-dimensional analytic modeling of very thin SOI MOSFET's
3. Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFET's down to 0.1 μm gate length
4. On the subthreshold swing and short channel effects in single and double gate deep submicron SOI-MOSFET
5. Buried oxide fringing capacitance: A new physical model and its implication on SOI device scaling and architecture
6. Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's
7. Threshold voltage model for deep-submicrometer MOSFETs
8. Capacitance network model of the short channel effect for 0.1 μm fully depleted SOI MOSFET