Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K

Solid-State Electronics

Volumn 41, Issue 1, 1997, Pages 111-119

  Pavanello, Marcelo Antonio ^a   Martino, João Antonio ^a   Colinge, Jean Pierre ^b  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; VOLTAGE CONTROL;

BACK GATE BIAS EFFECT MODEL; NUMERICAL BIDIMENSIONAL SIMULATION; SUBSTRATE POTENTIAL DROP; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 0030865493     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(96)00126-8     Document Type: Article

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