Electrical characterization and special properties of FinFET structures

NATO Security through Science Series C: Environmental Security

Volumn , Issue , 2007, Pages 199-220

  Rudenko, T ^a   Kilchytska, Valeria ^b   Collaert, N ^c   Nazarov, Alexei N ^a   Jurczak, M ^c   Flandre, Denis ^b  

^a INSTITUTE OF SEMICONDUCTOR PHYSICS   (Ukraine)

^b UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^c IMEC   (Belgium)

Author keywords

Effective channel mobility; FinFET; Gate tunneling current; Multi gate FETs; Silicon on insulator (SOI); Split CV technique

Indexed keywords

EID: 34548447197     PISSN: 18714668     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-1-4020-6380-0_15     Document Type: Conference Paper

References (20)

1. J. P. Colinge, Silicon-on-insulator Technology: Materials to VLSI (3-rd ed. Boston. MA: Kluwer, 2004).
2. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, FinFET - A self-aligned double-gate MOSFET scalable to 20 nm", IEEE Trans. Electron Devices, vol. 47, 2320-2325 (2000).
3. J.-T. Park, and J.-P. Colinge, Multi-gate SOI MOSFETs: Device design guidelines, IEEE Trans. Electron Devices, vol. 49, 2222-2229 (2002).
4. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, FinFET scaling to 10 nm gate length, in IEDM Tech. Dig., 251-254 (2002).
5. F. Daugé, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, and B.-Y. Nguyen, Coupling effects and channel separation in FinFETs, Solid-State Electronicss, vol. 48, 535-542 (2004).
6. V. Kilchytska, T. Rudenko, N. Collaert, R. Rooyackers, M. Jurczak, J.-P. Raskin and D. Flandre, Mobility characterization in FinFETs using split C-V technique, Proceedings of the ULIS 2005 Conference, Bologna, Italy, April 7-8, 2005, 117-120.
7. 2 and SiON gate dielectrics and TaN gate electrode, Microelectronic Engineering, vol. 80, 386-389 (2005).
8. K. Henson, N. Collaert, M. Demand et al, NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics, VLSI-TSA-TECH, April 2005, pp. 136-137.
9. 2 gate stack, Symposium on VLSI Technology, 108-109 (2005).
10. K. Romajek, F. Andrieu, T. Ernst, and G. Ghibaudo, Improved split C-V method for effective mobility extraction in sub-0.1-μm Si MOSFETs, IEEE Electron Device Letters, vol. 25, 583-585 (2004).
11. P. Zeitzoff, C. Young, G. Brown, and Y. Kim, Correcting effective mobility measurements for the presence of significant gate leakage current, IEEE Electron Device Letters, vol. 24, 275-277 (2003).
12. R. Ritzenthaler, S. Cristoloveanu, O. Faynot, C. Jahan, A. Kuriyama, L. Brevard, and S. Deleonibus, Lateral coupling and immunity to substrate effect in QFET devices, Solid-State Electronics, vol. 50, 558-565 (2006).
13. T. Rudenko, V. Kilchytska, N. Collaert, S. De Gendt, R. Rooyackers, M. Jurczak, and D. Flandre, Specific features of the capacitance and mobility behaviors in FinFET structures, Proceedings of ESSDERC 2005 Conference, Grenoble, France, 12-16 September 2005, 85-88 (2005).
14. F. Gámiz, J. B. Roldán, J. A. López- Villanueva, P. Cartujo -Cassinello, J.E. Carceller, P. Cartujo, F. Jiménez-Molinos, Electron transport in silicon-on-insulator devices, Solid-State Electronics, vol. 45, 613-620 (2001).
15. F. Gámiz, and M. V. Fischetti, Monte Carlo simulation of double-gate silicon-on-insulator inversion layers: The role of volume inversion, J. Appl. Phys. 89(10), 5478-5487 (2001).
16. D. Esseni, M. Mastrapasqua, G.K. Celler, F.H. Baumann, C. Fiegna, L. Selmi and E. Sangiorgi, Low field mobility of ultra-thin SOI n- and p-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs, in IEDM Tech. Dig., 671 -674 (2001).
17. K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm, in IEDM Tech. Dig., 47-50 (2002).
18. L. Chang, K. J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King, and C. Hu, Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs, in IEDM Tech. Dig., 99-102 (2001).
19. L. Chang, K. J. Yang, Y.-C. Yeo, I. Polishchuk, T.-J. King, and C. Hu, Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs, IEEE Trans. Electron Devices, vol. 49, pp. 2288-2295 (2002).
20. H. S. Momose, T. Ohguro, S.-I. Nakamura, Y. Toyoshima, H. Ishiuchi, and H. Iwai, Ultra-thin gate oxide CMOS on (111) surface oriented Si substrate, IEEE Trans. Electron Devices, vol. 49, 1597-1605 (2002).