Threshold voltage in ultra thin FDSOI CMOS: Advanced triple interface model and experimental devices

ULIS 2008 - 9th International Conference on ULtimate Integration of Silicon

Volumn , Issue , 2008, Pages 31-34

  Mazellier, J F ^a,b   Andrieu, F ^a   Faynot, O ^a   Brevard, L ^a   Buj, C ^a   Cristoloveanu, S ^b   Le Tiec, Y ^a   Deleonibus, S ^a  

^a CEA LETI   (France)

^b IMEP LAHC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

SILICON;

COUPLING MODELS; INTERFACE MODELING; INTERNATIONAL CONFERENCES; N-MOSFET; SOI-MOSFETS; ULTRA-THIN BODIES; VOLUME INVERSION;

NONMETALS;

EID: 49049103604     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ULIS.2008.4527135     Document Type: Conference Paper

References (8)

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4. R. Ranica, IEEE IEDM, 2004
5. I. Ban, IEEE IEDM, 2006
6. T. Shino, VLSI Symposium, 2004
7. H.K. Lim, IEEE Trans. Elec. Dev, 30(10)
8. F. Balestra, IEEE Trans. Elec. Dev, 37(11)