Testing of SoCs with hierarchical cores: Common fallacies, test access optimization, and test scheduling

IEEE Transactions on Computers

Volumn 58, Issue 3, 2009, Pages 409-423

  Goel, Sandeep Kumar ^a   Marinissen, Erik Jan ^b   Sehgal, Anuja ^c   Chakrabarty, Krishnendu ^d  

^a AGERE SYSTEMS   (United States)

^b IMEC   (Belgium)

^c NVIDIA   (United States)

^d Duke University   (United States)

Author keywords

Hierarchical SoCs; SoC test; TAMs and wrappers; Test architecture design; Test scheduling

Indexed keywords

AREA COST; HIERARCHICAL CORES; SOC TESTS; SYSTEM-ON-CHIP; TAM OPTIMIZATION; TEST ACCESS; TEST ACCESS MECHANISM; TEST APPLICATIONS; TEST ARCHITECTURE; TEST SCHEDULING; WRAPPER DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BENCHMARKING; MACHINE DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS;

TESTING;

EID: 73349086290     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.169     Document Type: Article

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