An SoC test scheduling algorithm using reconfigurable union wrappers

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 231-236

  Yoneda, Tomokazu ^a   Imanishi, Masahiro ^a   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Reconfigurable union wrapper; System on a chip; Test access mechanism; Test scheduling

Indexed keywords

BENCHMARKING; CHIP SCALE PACKAGES; HEURISTIC ALGORITHMS; SEMICONDUCTING SILICON;

RECONFIGURABLE UNION WRAPPERS; SYSTEM-ON-A-CHIP; TEST ACCESS MECHANISM;

SCHEDULING ALGORITHMS;

EID: 34548306883     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364596     Document Type: Conference Paper

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