SOC Test Architecture Design for Efficient Utilization of Test Bandwidth

ACM Transactions on Design Automation of Electronic Systems

Volumn 8, Issue 4, 2003, Pages 399-429

  Goel, Sandeep Kumar ^a   Marinissen, Erik Jan ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Bandwidth utilization; Idle bits; Lower bound; SOC test; TAM and wrapper design; Test scheduling

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTER ARCHITECTURE; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; SCHEDULING; SYSTEMS ANALYSIS;

SYSTEM CHIPS;

SEMICONDUCTOR DEVICE TESTING;

EID: 0142063562     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/944027.944029     Document Type: Article

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