Test resource partitioning and optimization for SOC designs

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 319-324

  Larsson, E ^a,b   Fujiwara, H ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Automatic testing; Built in self test; Design optimization; Embedded system; Energy consumption; Iterative methods; Laboratories; Scheduling; System testing; Wires

Indexed keywords

AUTOMATIC TESTING; DESIGN; ECOLOGY; EMBEDDED SYSTEMS; ENERGY UTILIZATION; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; LABORATORIES; SCHEDULING; SYSTEM-ON-CHIP; WIRE;

CORE-BASED DESIGN; DESIGN OPTIMIZATION; DEVELOPMENT PROCESS; OPTIMIZATION TECHNIQUES; SYSTEM TESTING; TEST ACCESS MECHANISM; TEST APPLICATION TIME; TEST RESOURCE PARTITIONING;

BUILT-IN SELF TEST;

EID: 84943549327     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197669     Document Type: Conference Paper

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