Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 610-619

  Waayers, Tom ^a   Morren, Richard ^a   Grandi, Roberto ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC EQUIPMENT TESTING; EMBEDDED SYSTEMS; INTELLECTUAL PROPERTY; ROBUSTNESS (CONTROL SYSTEMS); SILICON;

SCAN TESTS; TAM DAISY-CHAIN; TEST WRAPPERS;

MICROPROCESSOR CHIPS;

EID: 33847097279     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584022     Document Type: Conference Paper

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