Multiple-constraint driven system-on-chip test time optimization

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 21, Issue 6, 2005, Pages 599-611

  Pouget, Julien ^a,b   Larsson, Erik ^a,c   Peng, Zebo ^a,c,d,e  

^a LINKÖPING UNIVERSITY   (Sweden)

^b STMICROELECTRONICS   (France)

^c Design and Test Automation in Europe ^*

^d Embedded Systems Laboratory

^e IEEE

Author keywords

Multiple constraints; Power constraint; SOC testing; Test scheduling; Wrapper and TAM design

Indexed keywords

MULTIPLE CONSTRAINTS; POWER CONSTRAINT; SOC TESTING; TEST SCHEDULING; WRAPPER AND TAM DESIGN;

ALGORITHMS; CONSTRAINT THEORY; FAULT TOLERANT COMPUTER SYSTEMS; OPTIMIZATION; SCHEDULING; TESTING;

MICROPROCESSOR CHIPS;

EID: 27844496593     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10836-005-2911-4     Document Type: Conference Paper

References (16)

1. R.M. Chou, K.K. Saluja, and V.D. Agrawal, "Scheduling Tests for VLSI Systems Under Power Constraints," IEEE Transactions on VLSI Systems, vol. 5, no. 2, pp. 175-185, 1997.
2. E. Cota, L. Cairo, M. Lubaszewski, and A. Orailoglu, "Test Planning and Design Space Exploration in a Core-based Environment," in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Paris, France, 2002, pp. 478-485.
3. H-S Hsu, J-R Huang, K-L Cheng, C-W Wang, C-T Huang, and C-W Wu, "Test Scheduling and Test Access Architecture Optimization for System-on-Chip," in Proceedings of IEEE Asian Test Symposium (ATS), Tamuning, Guam, USA, 2002, pp. 411-416.
4. Y. Huang, S.M. Reddy, W-T Cheng, P. Reuter, N. Mukherjee, C-C Tsai, O. Samman, and Y. Zaidan, "Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm," in Proceedings IEEE of International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 74-82.
5. V. Iyengar, K. Chakrabarty, and E.J. Marinissen, "Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip," Journal of Electronic Testing; Theory and Applications (JETTA), pp. 213-230, 2002.
6. V. Iyengar K. Chakrabarty, and E.J. Marinissen, "Efficient Wrapper/TAM Co-Optimization for Large SOCs," in Proceedings of Design and Test in Europe (DATE), Paris, France, 2002, pp. 491-498.
7. V. Iyengar, K. Chakrabarty, and E.J. Marinissen, "On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization," in Proceedings of IEEE VLSI Test Symposium (VTS), Monterey, California, USA, 2002, pp. 253-258.
8. V. Iyengar, S.K. Goel, E.J. Marinissen, and K. Chakrabarty, "Test Resource Optimization for Multi-Site Testing of SOCs under ATE Memory Depth Constraints," in Proceedings of IEEE International Test Conference, Baltimore, MD, USA, 2002, pp. 1159-1168.
9. V. Iyengar, K. Chakrabarty, M.D. Krasniewski, and G.N. Kuma, "Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs," in Proceedings of IEEE VLSI Test Symposium (VTS), 2003, pp. 299-304.
10. S.K. Goel and E.J. Marinissen, "Cluster-Based Test Architecture Design for System-On-Chip," in Proceedings of IEEE VLSI Test Symposium (VTS), Monterey, California, USA, 2002, pp. 259-264.
11. S.K. Goel and E.J. Marinissen, "Effective and efficient test architecture design for SOCs," in Proceedings of IEEE International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 529-538.
12. S. Koranne, "On Test Scheduling for Core-based. SOCs," in Proceedings of International Conference on VLSI Design, Bangalore, India, 2002, pp 505-510.
13. S. Koranne and V. Iyengar, "On the use of k - tuples for SoC test schedule representation," in Proceedings of International Test Conference (ITC), Baltimore, MD, USA, 2002, pp. 539-548.
14. E.J. Marinissen, R. Kapur, and Y. Zorian, "On Using IEEE P1500 SECT for Test Plug-n-play," in Proceedings of IEEE International Test Conference (ITC), Atlantic City, NJ, USA, 2000, pp. 770-777.
15. J. Pouget, E. Larsson, Z. Peng, M.-L. Flottes, and B. Roureyre, "An Efficient Approach to SoC Wrapper Design, TAM configuration, and Test Scheduling," in Proceedings of IEEE European Test Workshop (ETW), Maastricht, The Nederlands, 2003, pp. 117-122.
16. J. Pouget, E. Larsson, and Z. Peng, "SOC Test Time Minimization Under Multiple Constraints," in Proceedings of Asian Test Symposium (ATS), Xian, China, 2003, pp. 312-317.