Test infrastructure design for the nexperia™ home platform PNX8550 system chip

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn , Issue , 2004, Pages 108-113

  Goel, Sandeep Kumar ^a   Chiu, Kuoshu ^b   Marinissen, Erik Jan ^a   Nguyen, Toan ^b   Oostdijk, Steven ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED DESIGN; EMBEDDED MEMORIES; SYSTEMS ON CHIP (SOC);

CMOS INTEGRATED CIRCUITS; CONSUMER ELECTRONICS; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT;

MICROPROCESSOR CHIPS;

EID: 3042654827     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269215     Document Type: Conference Paper

References (13)

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2. Yervant Zorian, Erik Jan Marinissen, and Sujit Dey. Testing Embedded-Core Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 130-143, Washington, DC, October 1998.
3. Erik Jan Marinissen and Harald Vranken. On the Role of DfT in IC-ATE Matching. In Digest of Papers of IEEE International Workshop on Test Resource Partitioning (TRP), Baltimore, MD, November 2001.
4. Santanu Dutta, Rune Jensen, and Alf Rieckmann. VIPER: A Multi-processor SOC for Advanced Set-Top Box and Digital TV Systems. IEEE Design & Test of Computers, 18(5):21-31, Sep-Oct 2001.
5. Bart Vermeulen, Steven Oostdijk, and Frank Bouwman. Test and Debug Strategy of the PNX8525 Nexperia™ Digital Video Platform System Chip. In Proceedings IEEE International Test Conference (ITC), pages 121-130, Baltimore, MD, October 2001.
6. Erik Jan Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, Washington, DC, October 1998.
7. Erik Jan Marinissen et al. On IEEE P1500's Standard for Embedded Core Test. Journal of Electronic Testing: Theory and Applications, 18(4/5):365-383, August 2002.
8. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores. Journal of Electronic Testing: Theory and Applications, 18(2):213-230, April 2002.
9. Sandeep Kumar Goel and Erik Jan Marinissen. SOC Test Architecture Design for Efficient Utilization of Test Bandwidth. ACM Transactions on Design Automation of Electronic Systems, 8(4): 399-429, October 2003.
10. Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In Proceedings IEEE International Test Conference (ITC), pages 519-528, Baltimore, MD, October 2002.
11. Joep Aerts and Erik Jan Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proceedings IEEE International Test Conference (ITC), pages 448-457, Washington, DC, October 1998.
12. Sandeep Kumar Goel and Erik Jan Marinissen. Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. In Proceedings Design, Automation, and Test in Europe (DATE), pages 738-743, Munich, Germany, March 2003.
13. Sandeep Kumar Goel and Erik Jan Marinissen. Control-Aware Test Architecture Design for Modular SOC Testing. In Proceedings IEEE European Test Workshop (ETW), pages 57-62, Maastricht, The Netherlands, May 2003.