Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 6, 2005, Pages 956-965

  Zhao, Dan ^a   Upadhyaya, Shambhu ^b  

^a University of Louisiana at Lafayette   (United States)

^b the State University of New York   (United States)

Author keywords

Adaptive test access mechanism (TAM) configuration; Dynamic test partitioning; Power constraint; System on chip (SoC) test; Test compatibility

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; CONSTRAINT THEORY; DESIGN FOR TESTABILITY; INTELLECTUAL PROPERTY; MICROPROCESSOR CHIPS; OPTIMIZATION;

ADAPTIVE TEST ACCESS MECHANISM (TAM) CONFIGURATION; DYNAMIC TEST PARTITIONING; POWER CONSTRAINTS; SYSTEM-ON-CHIP (SOC) TESTS; TEST COMPATIBILITY;

INTEGRATED CIRCUIT TESTING;

EID: 20444493098     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.847893     Document Type: Article

References (30)

1. I. Ghosh, S. Dey, and N. K. Jha, "A fast and low cost testing technique for core-based system-on-chip," in Proc. IEEE Design Automation Conf., 1998, pp. 542-547.
2. V. Immaneni and S. Raman, "Direct access test scheme-Design of block and core cells for embedded ASICs," in Proc. IEEE Int. Test Conf., 1990, pp. 488-492.
3. N. Touba and B. Pouya, "Using partial isolation rings to test core-based designs," IEEE Design Test Comput., vol. 14, no. 4, pp. 52-59, Oct./Dec. 1997.
4. P. Varma and S. Bhatia, "A structured test re-use methodology for core-based system chips," in Proc. IEEE Int. Test Conf., 1998, pp. 294-302.
5. E. J. Marinissen et al., "A structured and scalable mechanism for test access to embedded reusable cores," in Proc. IEEE Int. Test Conf., 1998, pp. 284-293.
6. E. J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, and L. Whetsel, "Toward a standard for embedded core test: An example," in Proc. IEEE Int. Test Conf., 1999, pp. 616-627.
7. J. Aerts and E. J. Marinissen, "Scan chain design for test time reduction in core-based ICs," in Proc. IEEE Int. Test Conf., 1998, pp. 448-457.
8. E. J. Marinissen, S. K. Goel, and M. Lousberg, "Wrapper design for embedded core test," in Proc. IEEE Int. Test Conf., 2000, pp. 911-920.
9. M. Nourani and C. Papachristou, "An ILP formulation to optimize test access mechanism in system-on-chip testing," in Proc. IEEE Int. Test Conf., 2000, pp. 902-910.
10. V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Test wrapper and test access mechanism co-optimization for system-on-a-chip," in Proc. IEEE Int. Test Conf., 2001, pp. 1023-1032.
11. S. Koranne and V. S. Choudhary, "Formulation of SoC test scheduling as a network transportation problem," in Proc. Design, Automation, Test Eur. Conf., Mar. 2002.
12. E. Larsson and Z. Peng, "An integrated system-on-chip test framework," in Proc. Design, Automation, Test Eur. Conf., Mar. 2001, pp. 138-144.
13. Y. Huang et al., "Resource allocation and test scheduling for concurrent test of core-based SoC design," in Proc. Asian Test Symp., Nov. 2001, pp. 265-270.
14. V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "On using rectangle packing for SoC wrapper/TAM co-optimization," in Proc. IEEE VLSI Test Symp., 2002, pp. 253-258.
15. S. K. Goel and E. J. Marinissen, "Effective and efficient test architecture design for SoCs," in Proc. IEEE Int. Test Conf., 2002, pp. 529-538.
16. Y. Huang et al., "Optimal core wrapper width selection and SoC test scheduling based on 3-D bin packing algorithm," in Proc. IEEE Int. Test Conf., 2002, pp. 74-82.
17. V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs," in Proc. IEEE/ACM Design Automation Conf., 2002, pp. 685-690.
18. Y. Zorian, "A distributed BIST control scheme for complex VLSI devices," in Proc. IEEE VLSI Test Symp., Apr. 1993, pp. 4-9.
19. R. M. Chou, K. K. Saluja, and V. D. Agrawal, "Scheduling tests for VLSI systems under power constraints," IEEE Trans. VLSI Syst., vol. 5, no. 2, pp. 175-185, Jun. 1997.
20. F. Brglez and H. Fujiwara, "A neutral netlist of ten combinational bench-mark circuits and a target simulator in fortran," in Proc. IEEE Int. Symp. Circuits Syst., 1985, pp. 695-698.
21. F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proc. IEEE Int. Symp. Circuits Syst., 1989, pp. 1929-1934.
22. I. Hamzaoglu and J. H. Patel, "Test set compaction algorithms for combinational circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1998, pp. 283-289.
23. M. S. Hsiao, E. M. Rudnick, and J. H. Patel, "K2: An estimator for peak sustainable power of VLSI circuits," in Proc. IEEE Int. Symp. Low-Power Electron. Design, 1997, pp. 178-183.
24. M. S. Hsiao, "Peak power estimation using genetic spot optimization for large VLSI circuits," in Proc. Design, Automation, Test Eur. Conf., 1999, pp. 175-179.
25. D. Zhao and S. Upadhyaya, "Dynamically partitioned test scheduling for SoCs under power constraints," in Proc. IEEE North Atlantic Test Workshop, May 2002, pp. 72-81.
26. J. A. Bondy and U. S. R. Murty, Graph Theory with Applications. New York: American Elsevier, 1977.
27. G. Chartrand and O. R. Oellermann, Applied and Algorithmic Graph Theory. New York: McGraw-Hill, 1993.
28. C. Bron and J. Kerbosch, "Finding all cliques of an undirected graph," Commun. ACM, vol. 16, pp. 575-577, 1973.
29. G. Craig, C. Kime, and K. Saluja, "Test scheduling and control for VLSI built-in self-test," IEEE Trans. Comput., vol. 37, no. 9, pp. 1099-1109, Sep. 1988.
30. E. J. Marinissen, V. Iyengar, and K. Chakrabarty, "A set of benchmarks for modular testing of SoCs," in Proc. IEEE Int. Test Conf., 2002, pp. 519-528.