The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

Materials Science in Semiconductor Processing

Volumn 11, Issue 5, 2008, Pages 205-213

  Vincent, B ^a   Damlencourt, J F ^a   Morand, Y ^b   Pouydebasque, A ^a   Le Royer, C ^a   Clavelier, L ^a   Dechoux, N ^b   Rivallin, P ^a   Nguyen, T ^c   Cristoloveanu, S ^c   Campidelli, Y ^b   Rouchon, D ^a   Mermoux, M ^d   Deleonibus, S ^a   Bensahel, D ^b   Billon, T ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c IMEP LAHC   (France)

^d LEPMI   (France)

Author keywords

Ge condensation technique; Germanium on insulator; SOI GeOI hybrid substrates

Indexed keywords

ADVANCED CMOS; COINTEGRATION; FULLY DEPLETED; GE CONDENSATION; GE CONDENSATION TECHNIQUE; GERMANIUM ON INSULATOR; GERMANIUM ON INSULATORS; HYBRID SUBSTRATES; KEY PARAMETERS; METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS; MOSFETS; SILICON GERMANIUM ON INSULATORS; SILICON-ON-INSULATOR SUBSTRATES; SOI-GEOI HYBRID SUBSTRATES; THICK SOI; TRANSISTOR LEVEL; ULTRA-THIN;

CELL MEMBRANES; CONDENSATION; ELECTRON BEAM LITHOGRAPHY; FABRICATION; FIELD EFFECT TRANSISTORS; METALLIC COMPOUNDS; MICROSTRIP DEVICES; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTING GERMANIUM; SILICON ON INSULATOR TECHNOLOGY;

SUBSTRATES;

EID: 70349787487     PISSN: 13698001     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mssp.2008.10.005     Document Type: Article

References (37)

1. Skotnicki T, Hutchby JA, King TJ, Wong HHP, Bœuf F. The end of CMOS scaling. IEEE Circuits Devices Mag, 2005; (January/February): 16.
2. Liu CW, Maikap S, Yu CY. Mobility enhancement technologies, recent progress using new materials, process-induced strain and package strain. IEEE Circuits Devices Mag 2005; (May/June): 21.
3. Nakaharai S., Tezuka T., Sugiyama N., Moriyama Y., and Takagi S. Characterization of 7 nm thick strained Ge on Insulator layer fabricated by Ge condensation technique. Appl Phys Lett 83 (2003) 3516
4. Takagi S., Tezuka T., Irisawa T., Nakaharai S., Numata T., Usuda K., et al. Device structures and carrier transport properties of advanced CMOS using high mobility channels. Solid State Electron 51 (2007) 526
5. Clavelier L., Deguet C., Le Royer C., Vincent B., Damlencourt J.F., Hartmann J.M., et al. Review of some critical aspects of Ge and GeOI substrates. ECS Trans 3 7 (2006) 789
6. Tezuka T., Sugiyama N., Mizuno T., Suzuki M., and Takagi S. A novel fabrication technique of ultrathin and relaxed SiGe buffer layers with high Ge fraction for sub-100 nm strained silicon on insulator MOSFETs. Jpn J Appl Phys 40 (2001) 2886
7. Tezuka T., Sugiyama N., and Takagi S. Fabrication of strained Si on ultrathin SiGe on insulator virtual substrate with a high Ge fraction. Appl Phys Lett 79 (2001) 1798
8. Ghosh B., Wang X., Fan X.F., Register L.F., and Banerjee S.K. Monte Carlo study of Germanium n and pMOSFETs. IEEE Trans Electron Devices 52 4 (2005) 547
9. Yang YJ, Chang ST, Liu CW. Electron mobility enhancement in strained Germanium nMOSFETs and impact of strain engineering in ballistic regime. In: Proceedings of VLSI technology, systems and application, 2007.
10. Yeo C.Y., Cho B.J., Gao F., Lee S.J., Lee M.H., Yu C.Y., et al. Electron mobility enhancement using ultrathin pure Ge on Si substrate. IEEE Electron Device Lett 26 10 (2005) 761
11. Tezuka T, Nakaharai S, Moriyama Y, Sugiyama N, Takagi SI. Selectively-formed high mobility SiGe-on-Insulator pMOSFETs with Ge-rich strained surface channels using local condensation technique. VLSI Technol Dig 2004; 198.
12. Tezuka T., Nakaharai S., Moriyama Y., Sugiyama N., and Takagi S. High mobility strained SiGe on Insulator pMOSFETs with Ge rich surface channels fabricated by local condensation technique. IEEE Electron Device Lett 26 (2005) 243
13. Damlencourt JF, Costa R. Patent E.N. 0601850, 2005.
14. Di Z., Zhang M., Liu W., Luo S., Song Z., Lin C., et al. Fabrication and mechanism of relaxed SiGe on insulator by modified Ge condensation. J Vac Sci Technol B 23 (2005) 1637
15. Vincent B., Damlencourt J.F., Delaye V., Gassilloud R., Clavelier L., and Morand Y. Stacking faults generation during relaxation of SGOI layers obtained by the Ge condensation technique. Appl Phys Lett 90 (2007) 074101
16. 2. Appl Phys Lett 30 (1976) 290
17. Nakaharai S., Tezuka T., Hirashita N., Toyoda E., Moriyama Y., Sugiyama N., et al. The generation of crystal defects in Ge on insulator (GOI) layers in the GE condensation process. Semicond Sci Technol 22 (2007) S103
18. Yin H., Hobart K.D., Kub F.J., Shieh S.R., Duffy T.S., and Sturm J.C. High germanium content SiGe islands formed on compliant oxide by SiGe oxidation. Appl Phys Lett 84 (2004) 3624
19. Clavelier L, Damlencourt JF, Leroyer C, French Patent FR 0701587, 2007.
20. Vincent B., Damlencourt J.F., Rivallin P., Nolot E., Licitra C., Morand Y., et al. Fabrication of SiGe on insulator substrates by a condensation technique: an experimental and modeling study. Semicond Sci Technol 22 (2007) 237
21. Nguyen Q.T., Damlencourt J.F., Vincent B., Clavelier L., Morand Y., Gentil P., et al. High quality Germanium-On-Insulator wafers with excellent hole mobility. Solid-State Electron 51 (2007) 1172
22. Damlencourt JF, Vincent B, Rivallin P, Holliger P, Rouchon D, Nolot E, et al., Fabrication of SiGe-On-insulator by improved Ge condensation technique. In: Conference of digest of international SiGe technology and device meeting (ISTDM), 2006, p. 202.
23. Damlencourt J.F., Campidelli Y., Roure M.C., Vincent B., Martinez E., Fillot F., et al. Epitaxial regrowth of Ge on SGOI and GeOI substrates obtained by Ge condensation. ECS Trans 6 4 (2007) 315
24. Shang H., Lee K.L., Kozlowski P., D'Emic C., Babich I., Sikorski E., et al. Self aligned n channel Germanium MOSFERs with a thin Ge oxunitride gate dielectric and tungsten gate. IEEE Electron Devices Lett 25 3 (2004) 135
25. Chui O., Kulig L., Moran J., and Tsai W. Germanium n type shallow junction activation dependences. Appl Phys Lett 87 9 (2005) 909
26. Damlencourt J.F., Campidelli Y., Vincent B., Nguyen Q.T., Le Royer C., Morand Y., et al. Influence of annealing treatements on the morphology and electrical properties of GeOI substrates obtained by Ge condensation. ECS Trans 6 1 (2007) 65
27. Leroyer C., Vincent B., Clavelier L., Damlencourt J.F., Tabone C., Batude P., et al., High-κ and Metal Gate p-MOSFETs on GeOI obtained by Ge enrichment: analysis of ON & OFF performances. Electron Devices Lett 29 (2008) 6
28. Tezuka T., Sugiyama N., Takagi S., and Kawakubo T. Dislocation free formation of relaxed SiGe on insulator layers. Appl Phys Lett 80 (2002) 3560
29. Tezuka T., Sugiyama N., and Takagi S. Dislocation free relaxed SiGe on insulator mesa structures fabricated by high temperature oxidation. J Appl Phys 94 (2003) 7553
30. Vincent B., Damlencourt J.F., Morand Y., Rouchon D., and Mermoux M. Ge enrichment technique on SiGe/SOI mesa islands: a localized GeOI structures fabrication method. ECS Trans 13 1 (2008) 235
31. Vincent B, Clavelier L, Damlencourt JF. Demand of French Patent EN 0760380, 27/12/2007.
32. Hui J., Chiu T.Y., Wong S., and Oldham W.B. Selective oxidation technologies for high density MS. IEEE Electron Device Lett EDL-2 (1981) 244
33. Tezuka T., Hirashita N., Moriyama Y., Nakaharai S., Sugiyama N., and Takagi S. Strain analysis in ultrathin SiGe on insulator layers formed from strained Si on insulator substrates by Ge condensation process. Appl Phys Lett 90 (2007) 181918
34. Friedt D.M., Hergenrother J.M., Topol A.W., Chang L., Sekaric L., Sleightt J.W., et al. Aggressively Scaled (0.143 pmZ) 6T-SRAM Cell for the 32 nm Node and Beyond. IEDM Tech Dig (2004) 261
35. Nguyen QT, Damlencourt JF, Vincent B, Loup V, Le Cunff Y, Gentil P, et al., SOI-GeOI hybrid substrates elaboration by Ge condensation: process and electrical properties. In: Proceeding of IEEE International SOI conference, 2008, p. 103.
36. Faynot O., Barna G., Ritzenthaler R., and Gidon P. Scaling of multiple gate fully depleted SOI transistors. Solid State Devices Mater Proc (2004) 764
37. Batail E, Monfray S, Rideau D, Szczap M, Loubet N, Skotnicki T, et al., Germanium-On-Nothing (GeON): an innovative technology for ultrathin Ge film integration. In: Proceedings of the ESSDERC 2007 conference, 2007, p. 450.