SCOPUS 정보 검색 플랫폼

Volumn 6, Issue 1, 2007, Pages 65-71

Influence of annealing treatments on the morphology and electrical properties of GeOI substrates obtained by Ge condensation

(8) Damlencourt, J F a Campidelli, Y b Nguyen, T c Vincent, B a LeRoyer, C a Morand, Y b Cristoloveanu, S c Clavelier, L a

a CEA LETI (France)

b STMICROELECTRONICS (France)

c IMEP LAHC (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; GERMANIUM; HOLE MOBILITY; LOGIC GATES; MORPHOLOGY;

ANNEALING PARAMETERS; ANNEALING TREATMENTS; BLOCKING CAPABILITY; ELECTRICALLY ACTIVE DEFECTS; EPITAXIAL THICKENING; FULL DEPLETION; GE CONDENSATION; SITU RESISTIVITY;

IODINE COMPOUNDS;

EID: 45849087308 PISSN: 19385862 EISSN: 19386737 Source Type: Conference Proceeding
DOI: 10.1149/1.2727388 Document Type: Conference Paper

Times cited : (7)

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