Stacking fault generation during relaxation of silicon germanium on insulator layers obtained by the Ge condensation technique

Applied Physics Letters

Volumn 90, Issue 7, 2007, Pages

  Vincent, B ^a   Damlencourt, J F ^a   Delaye, V ^a   Gassilloud, R ^a   Clavelier, L ^a   Morand, Y ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC INSULATORS; SEMICONDUCTING SILICON COMPOUNDS; STRAIN RATE; SUBSTRATES; TRANSMISSION ELECTRON MICROSCOPY;

INSULATOR SUBSTRATES; PARTIAL DISLOCATIONS; SILICON GERMANIUM; STACKING FAULT GENERATION;

STACKING FAULTS;

EID: 33847157265     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.2470722     Document Type: Article

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