메뉴 건너뛰기




Volumn 56, Issue 9, 2009, Pages 1908-1920

Delta-sigma A/D conversion via time-mode signal processing

Author keywords

A D conversion; CMOS; Delta sigma ( ) modulation; Low power; Small area; Time mode signal processing (TMSP)

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT DESIGN; MODULATION;

EID: 70349263530     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2010144     Document Type: Article
Times cited : (86)

References (54)
  • 2
    • 34547329490 scopus 로고    scopus 로고
    • A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters
    • H. Pekau, A. Yousif, and J. W. Haslett, "A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters," in Proc. IEEE Int. Symp. Circuits Syst., 2006, pp. 2373-2376.
    • (2006) Proc. IEEE Int. Symp. Circuits Syst , pp. 2373-2376
    • Pekau, H.1    Yousif, A.2    Haslett, J.W.3
  • 4
    • 0037248737 scopus 로고    scopus 로고
    • An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering
    • Jan
    • T. Watanabe, T. Mizuno, and Y. Makino, "An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering," IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 120-125, Jan. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.1 , pp. 120-125
    • Watanabe, T.1    Mizuno, T.2    Makino, Y.3
  • 5
    • 50549088629 scopus 로고    scopus 로고
    • Embedded measurement of GHz digital signals with time amplification in CMOS
    • Aug
    • M. Safi-Harb and G. W. Roberts, "Embedded measurement of GHz digital signals with time amplification in CMOS," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 7, pp. 1884-1896, Aug. 2008.
    • (2008) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.55 , Issue.7 , pp. 1884-1896
    • Safi-Harb, M.1    Roberts, G.W.2
  • 7
    • 23744476511 scopus 로고    scopus 로고
    • A time-based energy-efficient analog-to-digital converter
    • Aug
    • H. Y. Yang and R. Sarpeshkar, "A time-based energy-efficient analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1590-1601, Aug. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.8 , pp. 1590-1601
    • Yang, H.Y.1    Sarpeshkar, R.2
  • 9
    • 34547339903 scopus 로고    scopus 로고
    • A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator
    • J. Kim and S. Cho, "A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator," in Proc. IEEE Int. Symp. Circuits Syst., 2006, pp. 3934-3937.
    • (2006) Proc. IEEE Int. Symp. Circuits Syst , pp. 3934-3937
    • Kim, J.1    Cho, S.2
  • 10
    • 0030784975 scopus 로고    scopus 로고
    • Delta-sigma modulators using frequency modulated intermediate values
    • Jan
    • M. Hovin, A. Olsen, T. S. Lande, and C. Toumazou, "Delta-sigma modulators using frequency modulated intermediate values," IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 13-22, Jan. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.1 , pp. 13-22
    • Hovin, M.1    Olsen, A.2    Lande, T.S.3    Toumazou, C.4
  • 11
    • 44849118533 scopus 로고    scopus 로고
    • 0.2 V 0.44 uW 20 kHz analog to digital ΣΔ modulator with 57 fJ/conversion FoM
    • Montreux, Switzerland, Sept
    • U. Wismar, D. Wisland, and P. Andreani, "0.2 V 0.44 uW 20 kHz analog to digital ΣΔ modulator with 57 fJ/conversion FoM," in Proc. Eur. Solid-State Circuits Conf.,Montreux, Switzerland, Sept. 2006, pp. 187-190.
    • (2006) Proc. Eur. Solid-State Circuits Conf , pp. 187-190
    • Wismar, U.1    Wisland, D.2    Andreani, P.3
  • 12
    • 44849092543 scopus 로고    scopus 로고
    • 0.2 V 7.5 uW 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS
    • Munich, Germany, Sep
    • U. Wismar, D. Wisland, and P. Andreani, "0.2 V 7.5 uW 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS," in Proc. Eur. Solid-State Circuits Conf., Munich, Germany, Sep. 2007, pp. 206-209.
    • (2007) Proc. Eur. Solid-State Circuits Conf , pp. 206-209
    • Wismar, U.1    Wisland, D.2    Andreani, P.3
  • 13
    • 34548845842 scopus 로고    scopus 로고
    • Delta-sigma analog-to-digital conversion via time-mode signal processing
    • C. S. Taillefer and G. W. Roberts, "Delta-sigma analog-to-digital conversion via time-mode signal processing," in Proc. IEEE Int. Symp. Circuits Syst., 2007, pp. 13-16.
    • (2007) Proc. IEEE Int. Symp. Circuits Syst , pp. 13-16
    • Taillefer, C.S.1    Roberts, G.W.2
  • 14
    • 0030195866 scopus 로고    scopus 로고
    • A low-voltage, low-power CMOS delay element
    • Jul
    • G. Kim, M. K. Kim, B. S. Chang, and W. Kim, "A low-voltage, low-power CMOS delay element," IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 966-971, Jul. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.7 , pp. 966-971
    • Kim, G.1    Kim, M.K.2    Chang, B.S.3    Kim, W.4
  • 15
    • 0031628206 scopus 로고    scopus 로고
    • A low power, wide linear-range CMOS voltage-controlled oscillator
    • W. Rhee, "A low power, wide linear-range CMOS voltage-controlled oscillator," in Proc. IEEE Int. Symp. Circuits Syst., 1998, vol. 2, pp. 85-88.
    • (1998) Proc. IEEE Int. Symp. Circuits Syst , vol.2 , pp. 85-88
    • Rhee, W.1
  • 17
    • 0030290680 scopus 로고    scopus 로고
    • Low-jitter process-independent DLL and PLL based on self-biased techniques
    • Nov
    • J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.11 , pp. 1723-1732
    • Maneatis, J.G.1
  • 19
    • 0029694490 scopus 로고    scopus 로고
    • An overview of sigma-delta converters: How a 1-bit ADC achieves more than 16-bit resolution
    • Sept
    • P. M. Aziz, H. V. Sorensen, and J. Van der Spiegel, "An overview of sigma-delta converters: How a 1-bit ADC achieves more than 16-bit resolution," IEEE Signal Process. Mag., vol. 13, no. 1, pp. 61-84, Sept. 1996.
    • (1996) IEEE Signal Process. Mag , vol.13 , Issue.1 , pp. 61-84
    • Aziz, P.M.1    Sorensen, H.V.2    Van der Spiegel, J.3
  • 22
    • 0034478801 scopus 로고    scopus 로고
    • A high-performance multibit ΔΣ CMOS ADC
    • Dec
    • Y. Geerts, M. S. J. Steyaert, and W. Sansen, "A high-performance multibit ΔΣ CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1829-1840, Dec. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.12 , pp. 1829-1840
    • Geerts, Y.1    Steyaert, M.S.J.2    Sansen, W.3
  • 23
    • 0037818283 scopus 로고    scopus 로고
    • A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18- μm CMOS
    • Jul
    • R. Gaggl, A. Wiesbauer, G. Fritz, C. Schranz, and P. Pessl, "A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18- μm CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1105-1114, Jul. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.7 , pp. 1105-1114
    • Gaggl, R.1    Wiesbauer, A.2    Fritz, G.3    Schranz, C.4    Pessl, P.5
  • 24
    • 0029703087 scopus 로고    scopus 로고
    • A 5v single-chip delta-sigma audio A/D converter with 111 dB dynamic-range
    • I. Fujimori and K. Koyama, "A 5v single-chip delta-sigma audio A/D converter with 111 dB dynamic-range," in Proc. Custom Integr. Circuits Conf., 1996, pp. 415-418.
    • (1996) Proc. Custom Integr. Circuits Conf , pp. 415-418
    • Fujimori, I.1    Koyama, K.2
  • 25
    • 0034479805 scopus 로고    scopus 로고
    • A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8X oversampling ratio
    • Dec
    • I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S.Kosic, J. Cao, and S. L. Chan, "A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8X oversampling ratio," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1820-1828, Dec. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.12 , pp. 1820-1828
    • Fujimori, I.1    Longo, L.2    Hairapetian, A.3    Seiyama, K.4    Kosic, S.5    Cao, J.6    Chan, S.L.7
  • 26
    • 0030108394 scopus 로고    scopus 로고
    • A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC
    • Mar
    • R. T. Baird and T. S. Fiez, "A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 312-320, Mar. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.3 , pp. 312-320
    • Baird, R.T.1    Fiez, T.S.2
  • 27
    • 10444259730 scopus 로고    scopus 로고
    • A 25-MS/s 14-b 200-mW ΣΔ modulator in 0.18- μm CMOS
    • Dec
    • P. Balmelli and Q. Huang, "A 25-MS/s 14-b 200-mW ΣΔ modulator in 0.18- μm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2161-2169, Dec. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.12 , pp. 2161-2169
    • Balmelli, P.1    Huang, Q.2
  • 28
    • 0026400093 scopus 로고
    • A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion
    • Dec
    • B. P. Brandt and B. A. Wooley, "A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion," IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1746-1756, Dec. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.12 , pp. 1746-1756
    • Brandt, B.P.1    Wooley, B.A.2
  • 29
    • 0031333312 scopus 로고    scopus 로고
    • A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
    • Dec
    • T. L. Brooks, D. H. Robertson, D. F. Kelly, A. Del Muro, and S. W. Harston, "A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1896-1906, Dec. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.12 , pp. 1896-1906
    • Brooks, T.L.1    Robertson, D.H.2    Kelly, D.F.3    Del Muro, A.4    Harston, S.W.5
  • 31
  • 32
    • 29044435476 scopus 로고    scopus 로고
    • A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13- μm CMOS
    • Dec
    • L. Dorrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig, "A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13- μm CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2416-2427, Dec. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.12 , pp. 2416-2427
    • Dorrer, L.1    Kuttner, F.2    Greco, P.3    Torta, P.4    Hartig, T.5
  • 33
    • 0042697093 scopus 로고    scopus 로고
    • A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator
    • Aug
    • F. Gerfers, M. Ortmanns, and Y. Manoli, "A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1343-1352, Aug. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.8 , pp. 1343-1352
    • Gerfers, F.1    Ortmanns, M.2    Manoli, Y.3
  • 34
    • 0036503172 scopus 로고    scopus 로고
    • A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip bluetooth transceiver
    • Mar
    • J. Grilo, I. Galton, K. Wang, and R. G. Montemayor, "A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip bluetooth transceiver," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 271-278, Mar. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.3 , pp. 271-278
    • Grilo, J.1    Galton, I.2    Wang, K.3    Montemayor, R.G.4
  • 35
    • 0036908706 scopus 로고    scopus 로고
    • A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and - 105-dB IM3 distortion at a 1.5-MHz signal frequency
    • Dec
    • S. K. Gupta and V. Fong, "A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and - 105-dB IM3 distortion at a 1.5-MHz signal frequency," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1653-1661, Dec. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.12 , pp. 1653-1661
    • Gupta, S.K.1    Fong, V.2
  • 36
    • 0242696150 scopus 로고    scopus 로고
    • A 1.8-V 2-MS/s 13-bit ΔΣ A/D converter with pseudo data-weighted-averaging in 0.18 μm digital CMOS
    • A. Hamoui and K. Martin, "A 1.8-V 2-MS/s 13-bit ΔΣ A/D converter with pseudo data-weighted-averaging in 0.18 μm digital CMOS," in Proc. Custom Integr. Circuits Conf., 2003, pp. 119-122.
    • (2003) Proc. Custom Integr. Circuits Conf , pp. 119-122
    • Hamoui, A.1    Martin, K.2
  • 37
    • 0742286338 scopus 로고    scopus 로고
    • A 14-bit ΔΣ ADC with 8× OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process
    • Dec
    • R. Jiang and T. S. Fiez, "A 14-bit ΔΣ ADC with 8× OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 63-74, Dec. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.39 , Issue.1 , pp. 63-74
    • Jiang, R.1    Fiez, T.S.2
  • 39
    • 0032123891 scopus 로고    scopus 로고
    • A 15-b resolution 2-MHz nyquist rate ΔΣ ADC in a 1-μm CMOS technology
    • Jul
    • A. M. Marques, V. Peluso, M. S. J. Steyaert, and W. Sansen, "A 15-b resolution 2-MHz nyquist rate ΔΣ ADC in a 1-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1065-1075, Jul. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.7 , pp. 1065-1075
    • Marques, A.M.1    Peluso, V.2    Steyaert, M.S.J.3    Sansen, W.4
  • 40
    • 0344771175 scopus 로고    scopus 로고
    • A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology
    • Jun
    • F. Medeiro, B. Perez-Verdu, and A. Rodriguez-Vazquez, "A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology," IEEE J. Solid-State Circuits, vol. 343, no. 6, pp. 748-760, Jun. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.343 , Issue.6 , pp. 748-760
    • Medeiro, F.1    Perez-Verdu, B.2    Rodriguez-Vazquez, A.3
  • 41
    • 27644516988 scopus 로고    scopus 로고
    • Low power delta-sigma modulator for ADSL applications in a low-voltage CMOS technology
    • Oct
    • M. Safi-Harb and G. W. Roberts, "Low power delta-sigma modulator for ADSL applications in a low-voltage CMOS technology," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 10, pp. 2075-2089, Oct. 2005.
    • (2005) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.52 , Issue.10 , pp. 2075-2089
    • Safi-Harb, M.1    Roberts, G.W.2
  • 43
    • 29044447507 scopus 로고    scopus 로고
    • A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio
    • Dec
    • K. Nguyen, R. Adams, K. Sweetland, and H. Chen, "A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2408-2415, Dec. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.12 , pp. 2408-2415
    • Nguyen, K.1    Adams, R.2    Sweetland, K.3    Chen, H.4
  • 45
  • 47
    • 0031169153 scopus 로고    scopus 로고
    • A 1.8-V digital-audio sigma-delta modulator in a 0.8-μm CMOS
    • June
    • S. Rabii and B. A. Wooley, "A 1.8-V digital-audio sigma-delta modulator in a 0.8-μm CMOS," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 783-796, June 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.6 , pp. 783-796
    • Rabii, S.1    Wooley, B.A.2
  • 49
    • 0035693267 scopus 로고    scopus 로고
    • A 2.5-V sigma-delta modulator for broadband communications applications
    • Dec
    • K. Vleugels, S. Rabii, and B. A. Wooley, "A 2.5-V sigma-delta modulator for broadband communications applications," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1887-1899, Dec. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.12 , pp. 1887-1899
    • Vleugels, K.1    Rabii, S.2    Wooley, B.A.3
  • 50
    • 0037249016 scopus 로고    scopus 로고
    • A 113-dB DSD audio ADC using a density-modulated dithering scheme
    • Jan
    • C. B. Wang, S. Ishizuka, and B. Y. Liu, "A 113-dB DSD audio ADC using a density-modulated dithering scheme," IEEE J. Solid-State Circuits vol. 38, no. 1, pp. 114-119, Jan. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.1 , pp. 114-119
    • Wang, C.B.1    Ishizuka, S.2    Liu, B.Y.3
  • 52
    • 0027611063 scopus 로고
    • A 16-b 320-kHz CMOS A/D converter using two-stage third-order ΣΔ noise shaping
    • Jun
    • G. Yin, F. Stubbe, and W. Sansen, "A 16-b 320-kHz CMOS A/D converter using two-stage third-order ΣΔ noise shaping," IEEE J. Solid-State Circuits, vol. 28, no. 6, pp. 640-647, Jun. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.6 , pp. 640-647
    • Yin, G.1    Stubbe, F.2    Sansen, W.3
  • 53
    • 29044446154 scopus 로고    scopus 로고
    • A low-power multi-bit ΣΔ modulator in 90-nm digital CMOS without DEM
    • Dec
    • J. Yu and F. Maloberti, "A low-power multi-bit ΣΔ modulator in 90-nm digital CMOS without DEM," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2428-2436, Dec. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.12 , pp. 2428-2436
    • Yu, J.1    Maloberti, F.2
  • 54
    • 0032632072 scopus 로고    scopus 로고
    • Analog-to-digital converter survey and analysis
    • Apr
    • R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Sel. Areas Commun., vol. 17, no. 4, pp. 539-550, Apr. 1999.
    • (1999) IEEE J. Sel. Areas Commun , vol.17 , Issue.4 , pp. 539-550
    • Walden, R.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.