Low-jitter process-independent DLL and PLL based on self-biased techniques

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1723-1732

  Maneatis, John G ^a,b,c,d,e,f  

^a HEWLETT PACKARD ENTERPRISE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c STANFORD UNIVERSITY   (United States)

^d HEWLETT PACKARD LABORATORIES   (United States)

^e HEWLETT PACKARD COMPANY   (United States)

^f NONE

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE;

DAMPING FACTOR; DELAY LOCKED LOOP; SELF BIASED TECHNIQUES;

DIGITAL INTEGRATED CIRCUITS;

EID: 0030290680     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.1996.542317     Document Type: Article

References (6)

1. F. Gardner, "Charge-pump phase-lock loops," IEEE Trans. Commun., vol. COM-28, no. 11, pp. 1849-1858, Nov. 1980.
2. J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," in ISSCC 1996 Dig. Tech. Papers, Feb. 1996, pp. 130-131.
3. J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec. 1993.
4. I. Young et al., "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors," IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607, Nov. 1992.
5. D. Mijuskovic et al, "Cell-based fully integrated CMOS frequency synthesizers," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 271-279, Mar. 1994.
6. A. Waizman, "A delay line loop for frequency synthesis of de-skewed clock," in ISSCC 1994 Dig. Tech. Papers, Feb. 1994, pp. 298-299.