A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 12, 2005, Pages 2416-2426

  Dörrer, Lukas ^a   Kuttner, Franz ^a   Greco, Patrizia ^a   Torta, Patrick ^a,b   Hartig, Thomas ^a  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^b Mixed signals and Analog Design Group

Author keywords

Capacitive feedforward filter design; Continuoustime delta sigma ADC; Digital receiver; Dynamic element matching; Jitter tolerant; Low power; Multibit delta sigma ADC; Scrambling; Tracking ADC; UMTS

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; INTERPOLATION; JITTER; SIGNAL RECEIVERS; SIGNAL TO NOISE RATIO;

CAPACITIVE FEEDFORWARD FILTER DESIGN; CONTINUOUSTIME DELTA-SIGMA ADC; DYNAMIC ELEMENT MATCHING; JITTER TOLERANT; MULTIBIT DELTA-SIGMA ADC; TRACKING ADC;

CMOS INTEGRATED CIRCUITS;

EID: 29044435476     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.856282     Document Type: Conference Paper

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