A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 12, 2005, Pages 2398-2406

  Ahn, Gil Cho ^a,b,d   Chang, Dong Young ^a,b,e   Brown, Matthew E ^a,b,f   Ozaki, Naoto ^a,c,g   Youra, Hiroshi ^a,c,h   Yamamura, Ken ^a,c,i   Hamashita, Koichi ^a,c   Takasuka, Kaoru ^a,c,j   Temes, Gábor C ^a,b   Moon, Un Ku ^a,b,k  

^a IEEE   (United States)

^b Oregon State University   (United States)

^c Asahi Kasei Microsystems   (Japan)

^d Broadcom ^*  (Japan)

^e Engim Inc   (Japan)

^f HEWLETT PACKARD COMPANY   (United States)

^g Asahi Kasei Microsystems   (Japan)

^h Design and Development Center   (Japan)

ⁱ Asahi Kasei Microsystems   (Japan)

^j Asahi Kasei Microsystems   (Japan)

^k Technical Program Committee   (United States)

more..

Author keywords

Delta sigma ADC; Low voltage; Switched RC

Indexed keywords

DELTA-SIGMA ADC; FEED-FORWARD TOPOLOGY; LOW VOLTAGE; SWITCHED-RC;

BANDWIDTH; CMOS INTEGRATED CIRCUITS; MODULATORS; OPERATIONAL AMPLIFIERS; SWITCHING;

ANALOG TO DIGITAL CONVERSION;

EID: 29044444622     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.856286     Document Type: Conference Paper

References (16)

1. A. Abo and P. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
2. International Technology Roadmap for Semiconductors, Semiconductor Industry Association (2004). [Online]. Available: http://public.itrs.net/
3. Y. Nakagome et al., "A 1.5 V circuit technology for 64 Mb DRAMs," in Dig. Symp. VLSI Circuits, Jun. 1990, pp. 17-18.
4. T. Cho and P. Gray, "A 10 b 20 Msamples/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995.
5. J. Crols and M. Steyaert, "Switched opamp: An approach to realize full CMOS SC circuits at very low supply voltages," IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 936-942, Aug. 1994.
6. V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, and W. Sansen, "A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1887-1897, Dec. 1998.
7. A. Baschirotto and R. Castello, "A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing," IEEE J. Solid-State Circuits, vol. 32, pp. 1979-1986, Dec. 1997.
8. M. Waltari and K. Halonen, "1-V 9-bit pipelined switched-opamp," IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 129-134, Jan. 2001.
9. B. Vaz, J. Goes, and N. Paulino, "A l.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency," in Dig. Symp. VLSI Circuits, Jun. 2004, pp. 432-435.
10. M. Keskin, U. Moon, and G. Ternes, "A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset opamps," IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 817-823, Jul. 2002.
11. D. Chang, G. Ahn, and U. Moon, "A 0.9 V 9 mW 1 MSPS digitally calibrated ADC with 75 dB SFDR," in Dig. Symp. VLSI Circuits, Jun. 2003, pp. 67-70.
12. D. Chang and U. Moon, "A 1.4-V 10-bit 25 MSPS pipelined ADC using opamp-reset switching technique," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1401-1404, Aug. 2003.
13. R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters. New York: Wiley/IEEE Press, 2004.
14. J. Silva, U. Moon, J. Steensgaard, and G. Temes, "Wideband low-distortion delta-sigma ADC topology," Electron. Lett., vol. 37, no. 12, pp. 737-738, Jun. 2001.
15. I. Fujimori, K. Koyama, D. Trager, F. Tam, and L. Longo, "A 5 V single-chip delta-sigma audio A/D converter with 111 dB dynamic range," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 329-336. Mar. 1997.
16. L. Wu, M. Keskin, U. Moon, and G. Temes, "Efficient common-mode feedback circuits for pseudo-differential switched-capacitor stages," in Proc. IEEE Int. Symp. Circuits and Systems, vol. V, May 2000. pp. 445-448.