Comparison of contemporary CMOS ring oscillators

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2004, Pages 281-284

  Badillo, Dean A ^a,b   Kiaei, Sayfe ^b  

^a MOTOROLA INC   (United States)

^b ARIZONA STATE UNIVERSITY   (United States)

Author keywords

CMOS; Phase noise; Ring oscillators

Indexed keywords

DELAY CELL TOPOLOGIES; PHASE NOISES; RING OSCILLATORS;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DATA REDUCTION; DIFFERENTIAL AMPLIFIERS; ELECTRIC INVERTERS; ELECTRIC POWER UTILIZATION; SPURIOUS SIGNAL NOISE; TUNING;

OSCILLATORS (ELECTRONIC);

EID: 4444378173     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. I. Young, "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors", IEEE J. Solid-State Circuits, Vol. 27, No. 11, November 1992
2. A. Hajimiri, T. H. Lee, "A general theory of phase noise in electric oscillators", IEEE J. Solid-State Circuits, Vol. 33, No. 2, pp. 179-194, February 1998.
3. W. Van, H. C. Luong, "A 900-MHz CMOS Low-Phase Noise Voltage-Controlled Ring Oscillator", IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 48, No. 2, pp. 216-221, February 2001.
4. C. Park, B. Kim, "A Low-Noise, 900-MHz VCO in 0.6-μm CMOS", IEEE J. Solid-State Circuits, Vol. 34, No. 5, pp. 586-591, May 1999.
5. D. Badillo, S. Kiaei, "A Low Phase Noise 2.0V 900MHz CMOS Voltage Controlled Ring Oscillator", IEEE ISCAS Proceedings of the 2004 International Symposium on, To be published