Analog-to-digital conversion using noise shaping and time encoding

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 7, 2008, Pages 2026-2037

  Hernandez, Luis ^a   Prefasi, Enrique ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

Analog digital conversion; Pulse width modulation; Sigma delta modulation

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CONTINUOUS TIME SYSTEMS; DELTA MODULATION; DELTA SIGMA MODULATION; DIGITAL TO ANALOG CONVERSION; ENCODING (SYMBOLS); PULSE WIDTH MODULATION; RADIO RECEIVERS; SIGNAL ENCODING; VOLTAGE CONTROL;

BINARY SIGNALS; CONTINUOUS-TIME SIGMA-DELTA MODULATORS; FLASH ANALOG-TO-DIGITAL CONVERTERS; IRREGULAR SAMPLING; LOW VOLTAGE CMOS TECHNOLOGY; LOW VOLTAGE TECHNOLOGY; NOVEL ARCHITECTURE; SIGMA DELTA MODULATOR;

MODULATORS;

EID: 50549094753     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.918003     Document Type: Article

References (14)

1. M. Moyal, M. Groepl, H. Werker, G. Mitteregger, and J. Schambacher, "A 700/900 mW/channel CMOS dual analog front end IC for VDSL with integrated 11.5/14.5 dBm line drivers," in Proc. ISSCC, 2003, vol. 1, pp. 416-504.
2. S. Paton, A. Giandomenico, L. Hernandez, A. Di Wiesbauer, T. Potscher, and M. Clara, "A 70-mW 300-MHz CMOS continuous-time sigma delta ADC with 15-MHz bandwidth and 11 bits of resolution," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1056-1063, Jul. 2004.
3. L. Dörrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig, "A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13- μm CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2416-2427, Dec. 2005.
4. F. Gerfers, M. Ortmanns, and Y. Manoli, "A 1.5 V 12 Bit power-efficient continuous-time third-order sigma delta modulator," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1343-1352, Aug. 2003.
5. E. Roza, "Analog-to-digital conversion via duty-cycle modulation," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 11, pp. 907-914, Nov. 1997.
6. S. Ouzounov, E. Roza, H. Hegt, G. van der Weide, and A. van Roermund, "An 8 MHz, 72 dB SFDR asynchronous sigma-delta modulator with 1.5 mW power dissipation," in Dig. Tech. Papers VLSI Circuits, 2004.
7. A. A. Lazar and L. T. Toth, "Time encoding and perfect recovery of bandlimited signals," in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., Apr. 6-10, 2003, vol. 6, pp. VI-709-VI-712.
8. S. Ouzounov, H. Hegt, and A. van Roermund, "Sigma-delta modulators operating at a limit cycle," IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 53, no. 5, pp. 399-403, May 2006.
9. A. A. Lazar, E. K. Simonyi, and L. T. Toth, Fast Recovery Algorithms for Time Encoded Bandlimited Signals Dep. Elect. Eng., Columbia Univ., New York, 2004, BNET Tech. Rep.
10. J. R. Higgins and R. L. Stens, Sampling Theory in Fourier and Signal Analysis. Oxford, U.K.: Oxford Univ. Press, 1996.
11. Z. Cvetkovic and M. Vetterli, "Error-rate characteristics of oversampled analog-to-digital conversion," IEEE Trans. Inf. Theory vol. 44, no. 5, pp. 1961-1964, Sep. 1998.
12. H. K. Khalil, Nonlinear Systems. New York: Macmillan, 1992.
13. R. W. Schafer and L. R. Rabiner, "A digital signal processing approach to interpolation," Proc. IEEE, vol. 61, no. 6, pp. 692-702, Jun. 1973.
14. P. Thevenaz, T. Blu, and M. Unser, "Interpolation revisited," IEEE Trans. Med. Imaging, vol. 19, no. 7, pp. 739-758, Jul. 2000.